arm64: dts: meson: sync dt and bindings from v5.7-rc1

[oweals/u-boot.git] / arch / arm / dts / meson-gx.dtsi

diff --git a/arch/arm/dts/meson-gx.dtsi b/arch/arm/dts/meson-gx.dtsi
index 40db06e28b662f85e1d20c12fd1fe52f7ad85680..03f79fe045b7f191216af87249b6a4aea2353379 100644 (file)
--- a/arch/arm/dts/meson-gx.dtsi
+++ b/arch/arm/dts/meson-gx.dtsi
@@ -12,6 +12,7 @@
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
 
 / {
        interrupt-parent = <&gic>;
@@ -83,6 +84,7 @@
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
+                       #cooling-cells = <2>;
                };
 
                cpu1: cpu@1 {
@@ -92,6 +94,7 @@
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
+                       #cooling-cells = <2>;
                };
 
                cpu2: cpu@2 {
@@ -101,6 +104,7 @@
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
+                       #cooling-cells = <2>;
                };
 
                cpu3: cpu@3 {
@@ -110,6 +114,7 @@
                        enable-method = "psci";
                        next-level-cache = <&l2>;
                        clocks = <&scpi_dvfs 0>;
+                       #cooling-cells = <2>;
                };
 
                l2: l2-cache0 {
@@ -117,6 +122,53 @@
                };
        };
 
+       thermal-zones {
+               cpu-thermal {
+                       polling-delay-passive = <250>; /* milliseconds */
+                       polling-delay = <1000>; /* milliseconds */
+
+                       thermal-sensors = <&scpi_sensors 0>;
+
+                       trips {
+                               cpu_passive: cpu-passive {
+                                       temperature = <80000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "passive";
+                               };
+
+                               cpu_hot: cpu-hot {
+                                       temperature = <90000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "hot";
+                               };
+
+                               cpu_critical: cpu-critical {
+                                       temperature = <110000>; /* millicelsius */
+                                       hysteresis = <2000>; /* millicelsius */
+                                       type = "critical";
+                               };
+                       };
+
+                       cpu_cooling_maps: cooling-maps {
+                               map0 {
+                                       trip = <&cpu_passive>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+
+                               map1 {
+                                       trip = <&cpu_hot>;
+                                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                                        <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+                               };
+                       };
+               };
+       };
+
        arm-pmu {
                compatible = "arm,cortex-a53-pmu";
                interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,