Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1043a-rdb.dts

diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 17a06812c571942bdc8d67f72c3e51257fe68b3f..6e4ea5b40c7858d99f4023e161f4db16fc20729a 100644 (file)
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -1,13 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
+ * Copyright 2020 NXP
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 /dts-v1/;
@@ -15,6 +13,25 @@
 
 / {
        model = "LS1043A RDB Board";
+
+        aliases {
+               spi1 = &dspi0;
+        };
+
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dspiflash: n25q12a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <1000000>; /* input clock */
+       };
+
 };
 
 &i2c0 {
@@ -28,12 +45,12 @@
                compatible = "adi,adt7461a";
                reg = <0x4c>;
        };
-       eeprom@56 {
+       eeprom@52 {
                compatible = "at24,24c512";
                reg = <0x52>;
        };
 
-       eeprom@57 {
+       eeprom@53 {
                compatible = "at24,24c512";
                reg = <0x53>;
        };
@@ -50,8 +67,8 @@
        #size-cells = <1>;
        /* NOR, NAND Flashes and FPGA on board */
        ranges = <0x0 0x0 0x0 0x60000000 0x08000000
-                 0x2 0x0 0x0 0x7e800000 0x00010000
-                 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+                 0x1 0x0 0x0 0x7e800000 0x00010000
+                 0x2 0x0 0x0 0x7fb00000 0x00000100>;
 
                nor@0,0 {
                        compatible = "cfi-flash";
@@ -82,3 +99,83 @@
 &duart1 {
        status = "okay";
 };
+
+#include "fsl-ls1043-post.dtsi"
+
+&fman0 {
+       ethernet@e0000 {
+               phy-handle = <&qsgmii_phy1>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@e2000 {
+               phy-handle = <&qsgmii_phy2>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@e4000 {
+               phy-handle = <&rgmii_phy1>;
+               phy-connection-type = "rgmii-txid";
+               status = "okay";
+       };
+
+       ethernet@e6000 {
+               phy-handle = <&rgmii_phy2>;
+               phy-connection-type = "rgmii-txid";
+               status = "okay";
+       };
+
+       ethernet@e8000 {
+               phy-handle = <&qsgmii_phy3>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@ea000 {
+               phy-handle = <&qsgmii_phy4>;
+               phy-connection-type = "qsgmii";
+               status = "okay";
+       };
+
+       ethernet@f0000 { /* 10GEC1 */
+               phy-handle = <&aqr105_phy>;
+               phy-connection-type = "xgmii";
+               status = "okay";
+       };
+
+       mdio@fc000 {
+               rgmii_phy1: ethernet-phy@1 {
+                       reg = <0x1>;
+               };
+
+               rgmii_phy2: ethernet-phy@2 {
+                       reg = <0x2>;
+               };
+
+               qsgmii_phy1: ethernet-phy@4 {
+                       reg = <0x4>;
+               };
+
+               qsgmii_phy2: ethernet-phy@5 {
+                       reg = <0x5>;
+               };
+
+               qsgmii_phy3: ethernet-phy@6 {
+                       reg = <0x6>;
+               };
+
+               qsgmii_phy4: ethernet-phy@7 {
+                       reg = <0x7>;
+               };
+       };
+
+       mdio@fd000 {
+               aqr105_phy: ethernet-phy@1 {
+                       compatible = "ethernet-phy-ieee802.3-c45";
+                       interrupts = <0 132 4>;
+                       reg = <0x1>;
+               };
+       };
+};