SPDX: Convert all of our multiple license tags to Linux Kernel style

[oweals/u-boot.git] / arch / arm / dts / fsl-ls1043a-qds.dtsi

diff --git a/arch/arm/dts/fsl-ls1043a-qds.dtsi b/arch/arm/dts/fsl-ls1043a-qds.dtsi
index b9dad72d45777878c30340f7acd509cabcbb879b..addb9abfb9324d4118653fce8fb1b444bb921d3f 100644 (file)
--- a/arch/arm/dts/fsl-ls1043a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1043a-qds.dtsi
@@ -1,19 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 /include/ "fsl-ls1043a.dtsi"
 
 / {
        model = "LS1043A QDS Board";
+       aliases {
+               spi0 = &qspi;
+               spi1 = &dspi0;
+       };
+};
+
+&dspi0 {
+       bus-num = <0>;
+       status = "okay";
+
+       dflash0: n25q128a {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <1000000>; /* input clock */
+               spi-cpol;
+               spi-cpha;
+               reg = <0>;
+       };
+
+       dflash1: sst25wf040b {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               spi-cpol;
+               spi-cpha;
+               reg = <1>;
+       };
+
+       dflash2: en25s64 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <3500000>;
+               spi-cpol;
+               spi-cpha;
+               reg = <2>;
+       };
+};
+
+&qspi {
+       bus-num = <0>;
+       status = "okay";
+
+       qflash0: s25fl128s@0 {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "spi-flash";
+               spi-max-frequency = <20000000>;
+               reg = <0>;
+       };
 };
 
 &i2c0 {
@@ -83,8 +132,8 @@
        #size-cells = <1>;
        /* NOR, NAND Flashes and FPGA on board */
        ranges = <0x0 0x0 0x0 0x60000000 0x08000000
-                 0x2 0x0 0x0 0x7e800000 0x00010000
-                 0x3 0x0 0x0 0x7fb00000 0x00000100>;
+                 0x1 0x0 0x0 0x7e800000 0x00010000
+                 0x2 0x0 0x0 0x7fb00000 0x00000100>;
        status = "okay";
 
        nor@0,0 {
@@ -96,21 +145,21 @@
                device-width = <1>;
        };
 
-       nand@2,0 {
+       nand@1,0 {
                compatible = "fsl,ifc-nand";
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x1 0x0 0x10000>;
        };
 
-       fpga: board-control@3,0 {
+       fpga: board-control@2,0 {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "simple-bus";
-               reg = <0x3 0x0 0x0000100>;
+               reg = <0x2 0x0 0x0000100>;
                bank-width = <1>;
                device-width = <1>;
-               ranges = <0 3 0 0x100>;
+               ranges = <0 2 0 0x100>;
        };
 };