Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[oweals/u-boot.git] / arch / arm / cpu / armv8 / cache_v8.c

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index bd1c3e0335d4630f8367581fb88a864a0964b621..7c31d98a6f03157af1d72f28fe9c0162cdb7d02f 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -1,20 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * (C) Copyright 2013
  * David Feng <fenghua@phytium.com.cn>
  *
  * (C) Copyright 2016
  * Alexander Graf <agraf@suse.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <log.h>
+#include <asm/cache.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  *  With 4k page granule, a virtual address is split into 4 lookup parts
@@ -230,7 +233,10 @@ static void add_map(struct mm_region *map)
                                /* Page fits, create block PTE */
                                debug("Setting PTE %p to block virt=%llx\n",
                                      pte, virt);
-                               *pte = phys | attrs;
+                               if (level == 3)
+                                       *pte = phys | attrs | PTE_TYPE_PAGE;
+                               else
+                                       *pte = phys | attrs;
                                virt += blocksize;
                                phys += blocksize;
                                size -= blocksize;
@@ -441,12 +447,13 @@ inline void flush_dcache_all(void)
                debug("flushing dcache successfully.\n");
 }
 
+#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
 /*
  * Invalidates range in all levels of D-cache/unified cache
  */
 void invalidate_dcache_range(unsigned long start, unsigned long stop)
 {
-       __asm_flush_dcache_range(start, stop);
+       __asm_invalidate_dcache_range(start, stop);
 }
 
 /*
@@ -456,6 +463,15 @@ void flush_dcache_range(unsigned long start, unsigned long stop)
 {
        __asm_flush_dcache_range(start, stop);
 }
+#else
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
 
 void dcache_enable(void)
 {
@@ -541,7 +557,7 @@ static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
                                     enum dcache_option option)
 {
-       u64 attrs = PMD_ATTRINDX(option);
+       u64 attrs = PMD_ATTRINDX(option >> 2);
        u64 real_start = start;
        u64 real_size = size;
 
@@ -645,7 +661,7 @@ void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
        __asm_invalidate_tlb_all();
 }
 
-#else  /* CONFIG_SYS_DCACHE_OFF */
+#else  /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
 /*
  * For SPL builds, we may want to not have dcache enabled. Any real U-Boot
@@ -682,9 +698,9 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 {
 }
 
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
 
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
 
 void icache_enable(void)
 {
@@ -708,7 +724,7 @@ void invalidate_icache_all(void)
        __asm_invalidate_l3_icache();
 }
 
-#else  /* CONFIG_SYS_ICACHE_OFF */
+#else  /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 void icache_enable(void)
 {
@@ -727,7 +743,7 @@ void invalidate_icache_all(void)
 {
 }
 
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
 
 /*
  * Enable dCache & iCache, whether cache is actually enabled