+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2013
* David Feng <fenghua@phytium.com.cn>
*
* (C) Copyright 2016
* Alexander Graf <agraf@suse.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cpu_func.h>
+#include <hang.h>
+#include <log.h>
+#include <asm/cache.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* With 4k page granule, a virtual address is split into 4 lookup parts
/* Page fits, create block PTE */
debug("Setting PTE %p to block virt=%llx\n",
pte, virt);
- *pte = phys | attrs;
+ if (level == 3)
+ *pte = phys | attrs | PTE_TYPE_PAGE;
+ else
+ *pte = phys | attrs;
virt += blocksize;
phys += blocksize;
size -= blocksize;
static void setup_all_pgtables(void)
{
u64 tlb_addr = gd->arch.tlb_addr;
+ u64 tlb_size = gd->arch.tlb_size;
/* Reset the fill ptr */
gd->arch.tlb_fillptr = tlb_addr;
setup_pgtables();
/* Create emergency page tables */
+ gd->arch.tlb_size -= (uintptr_t)gd->arch.tlb_fillptr -
+ (uintptr_t)gd->arch.tlb_addr;
gd->arch.tlb_addr = gd->arch.tlb_fillptr;
setup_pgtables();
gd->arch.tlb_emerg = gd->arch.tlb_addr;
gd->arch.tlb_addr = tlb_addr;
+ gd->arch.tlb_size = tlb_size;
}
/* to activate the MMU we need to set up virtual memory */
void invalidate_dcache_all(void)
{
__asm_invalidate_dcache_all();
+ __asm_invalidate_l3_dcache();
}
/*
* Performs a clean & invalidation of the entire data cache at all levels.
* This function needs to be inline to avoid using stack.
- * __asm_flush_l3_cache return status of timeout
+ * __asm_flush_l3_dcache return status of timeout
*/
inline void flush_dcache_all(void)
{
int ret;
__asm_flush_dcache_all();
- ret = __asm_flush_l3_cache();
+ ret = __asm_flush_l3_dcache();
if (ret)
debug("flushing dcache returns 0x%x\n", ret);
else
debug("flushing dcache successfully.\n");
}
+#ifndef CONFIG_SYS_DISABLE_DCACHE_OPS
/*
* Invalidates range in all levels of D-cache/unified cache
*/
void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- __asm_flush_dcache_range(start, stop);
+ __asm_invalidate_dcache_range(start, stop);
}
/*
{
__asm_flush_dcache_range(start, stop);
}
+#else
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+
+void flush_dcache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif /* CONFIG_SYS_DISABLE_DCACHE_OPS */
void dcache_enable(void)
{
return !(addr & (align - 1)) && !(size & (align - 1));
}
-static u64 set_one_region(u64 start, u64 size, u64 attrs, int level)
+/* Use flag to indicate if attrs has more than d-cache attributes */
+static u64 set_one_region(u64 start, u64 size, u64 attrs, bool flag, int level)
{
int levelshift = level2shift(level);
u64 levelsize = 1ULL << levelshift;
/* Can we can just modify the current level block PTE? */
if (is_aligned(start, size, levelsize)) {
- *pte &= ~PMD_ATTRINDX_MASK;
- *pte |= attrs;
+ if (flag) {
+ *pte &= ~PMD_ATTRMASK;
+ *pte |= attrs & PMD_ATTRMASK;
+ } else {
+ *pte &= ~PMD_ATTRINDX_MASK;
+ *pte |= attrs & PMD_ATTRINDX_MASK;
+ }
debug("Set attrs=%llx pte=%p level=%d\n", attrs, pte, level);
return levelsize;
void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
enum dcache_option option)
{
- u64 attrs = PMD_ATTRINDX(option);
+ u64 attrs = PMD_ATTRINDX(option >> 2);
u64 real_start = start;
u64 real_size = size;
u64 r;
for (level = 1; level < 4; level++) {
- r = set_one_region(start, size, attrs, level);
+ /* Set d-cache attributes only */
+ r = set_one_region(start, size, attrs, false, level);
if (r) {
/* PTE successfully replaced */
size -= r;
flush_dcache_range(real_start, real_start + real_size);
}
-#else /* CONFIG_SYS_DCACHE_OFF */
+/*
+ * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits.
+ * The procecess is break-before-make. The target region will be marked as
+ * invalid during the process of changing.
+ */
+void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs)
+{
+ int level;
+ u64 r, size, start;
+
+ start = addr;
+ size = siz;
+ /*
+ * Loop through the address range until we find a page granule that fits
+ * our alignment constraints, then set it to "invalid".
+ */
+ while (size > 0) {
+ for (level = 1; level < 4; level++) {
+ /* Set PTE to fault */
+ r = set_one_region(start, size, PTE_TYPE_FAULT, true,
+ level);
+ if (r) {
+ /* PTE successfully invalidated */
+ size -= r;
+ start += r;
+ break;
+ }
+ }
+ }
+
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ __asm_invalidate_tlb_all();
+
+ /*
+ * Loop through the address range until we find a page granule that fits
+ * our alignment constraints, then set it to the new cache attributes
+ */
+ start = addr;
+ size = siz;
+ while (size > 0) {
+ for (level = 1; level < 4; level++) {
+ /* Set PTE to new attributes */
+ r = set_one_region(start, size, attrs, true, level);
+ if (r) {
+ /* PTE successfully updated */
+ size -= r;
+ start += r;
+ break;
+ }
+ }
+ }
+ flush_dcache_range(gd->arch.tlb_addr,
+ gd->arch.tlb_addr + gd->arch.tlb_size);
+ __asm_invalidate_tlb_all();
+}
+
+#else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
/*
* For SPL builds, we may want to not have dcache enabled. Any real U-Boot
{
}
-#endif /* CONFIG_SYS_DCACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
void icache_enable(void)
{
- __asm_invalidate_icache_all();
+ invalidate_icache_all();
set_sctlr(get_sctlr() | CR_I);
}
void invalidate_icache_all(void)
{
__asm_invalidate_icache_all();
+ __asm_invalidate_l3_icache();
}
-#else /* CONFIG_SYS_ICACHE_OFF */
+#else /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
void icache_enable(void)
{
{
}
-#endif /* CONFIG_SYS_ICACHE_OFF */
+#endif /* !CONFIG_IS_ENABLED(SYS_ICACHE_OFF) */
/*
* Enable dCache & iCache, whether cache is actually enabled
projects / oweals / u-boot.git / blobdiff