common: Drop linux/delay.h from common header

[oweals/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / cpu.c

diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 1a640bbb9c2c642a4ad11ca8e5400e5263f6c266..91e988217ad4a63514d5c744c057212df97e78d6 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -1,10 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <net.h>
+#include <vsprintf.h>
 #include <asm/arch/clock.h>
 #include <asm/io.h>
 #include <asm/arch/immap_ls102xa.h>
@@ -13,6 +16,9 @@
 #include <tsec.h>
 #include <netdev.h>
 #include <fsl_esdhc.h>
+#include <config.h>
+#include <fsl_wdog.h>
+#include <linux/delay.h>
 
 #include "fsl_epu.h"
 
@@ -25,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
 
 /*
  * Bit[1] of the descriptor indicates the descriptor type,
@@ -214,7 +220,15 @@ void enable_caches(void)
        invalidate_dcache_all();
        set_cr(get_cr() | CR_C);
 }
-#endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
+#endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
+
+
+uint get_svr(void)
+{
+       struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+
+       return in_be32(&gur->svr);
+}
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
@@ -287,7 +301,7 @@ int cpu_mmc_init(bd_t *bis)
 
 int cpu_eth_init(bd_t *bis)
 {
-#ifdef CONFIG_TSEC_ENET
+#if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
        tsec_standard_init(bis);
 #endif
 
@@ -299,6 +313,7 @@ int arch_cpu_init(void)
        void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
        void *rcpm2_base =
                (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
+       struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
        u32 state;
 
        /*
@@ -326,10 +341,12 @@ int arch_cpu_init(void)
         */
        fsl_epu_clean(epu_base);
 
+       setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
+
        return 0;
 }
 
-#if defined(CONFIG_ARMV7_NONSEC) || defined(CONFIG_ARMV7_VIRT)
+#ifdef CONFIG_ARMV7_NONSEC
 /* Set the address at which the secondary core starts from.*/
 void smp_set_core_boot_addr(unsigned long addr, int corenr)
 {
@@ -344,5 +361,36 @@ void smp_kick_all_cpus(void)
        struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 
        out_be32(&gur->brrl, 0x2);
+
+       /*
+        * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
+        * So add a delay to wait bootrom execute WFE.
+        */
+       udelay(1);
+
+       asm volatile("sev");
 }
 #endif
+
+void reset_cpu(ulong addr)
+{
+       struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
+
+       clrbits_be16(&wdog->wcr, WCR_SRS);
+
+       while (1) {
+               /*
+                * Let the watchdog trigger
+                */
+       }
+}
+
+void arch_preboot_os(void)
+{
+       unsigned long ctrl;
+
+       /* Disable PL1 Physical Timer */
+       asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
+       ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+       asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
+}