ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / cpu / arm926ejs / lpc32xx / cpu.c

diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
index e29e130338f9c03477f03ad6d7619f14ffb0856a..4c59a44f7e6c31d261fade7cae4a42d73b6e2692 100644 (file)
--- a/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
@@ -1,26 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
+ * Copyright (C) 2011-2015 by Vladimir Zapolskiy <vz@mleia.com>
  */
 
 #include <common.h>
+#include <cpu_func.h>
+#include <netdev.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/wdt.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 
 static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
@@ -31,12 +20,23 @@ void reset_cpu(ulong addr)
        /* Enable watchdog clock */
        setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
 
-       /* Reset pulse length is 13005 peripheral clock frames */
-       writel(13000, &wdt->pulse);
+       /* To be compatible with the original U-Boot code:
+        * addr: - 0: perform hard reset.
+        *       - !=0: perform a soft reset; i.e. "RESOUT_N" not asserted). */
+       if (addr == 0) {
+               /* Reset pulse length is 13005 peripheral clock frames */
+               writel(13000, &wdt->pulse);
 
-       /* Force WDOG_RESET2 and RESOUT_N signal active */
-       writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1 | WDTIM_MCTRL_M_RES2,
-              &wdt->mctrl);
+               /* Force WDOG_RESET2 and RESOUT_N signal active */
+               writel(WDTIM_MCTRL_RESFRC2 | WDTIM_MCTRL_RESFRC1
+                      | WDTIM_MCTRL_M_RES2, &wdt->mctrl);
+       } else {
+               /* Force match output active */
+               writel(0x01, &wdt->emr);
+
+               /* Internal reset on match output (no pulse on "RESOUT_N") */
+               writel(WDTIM_MCTRL_M_RES1, &wdt->mctrl);
+       }
 
        while (1)
                /* NOP */;
@@ -46,7 +46,7 @@ void reset_cpu(ulong addr)
 int arch_cpu_init(void)
 {
        /*
-        * It might be necessary to flush data cache, if U-boot is loaded
+        * It might be necessary to flush data cache, if U-Boot is loaded
         * from kickstart bootloader, e.g. from S1L loader
         */
        flush_dcache_all();
@@ -68,3 +68,11 @@ int print_cpuinfo(void)
        return 0;
 }
 #endif
+
+#ifdef CONFIG_LPC32XX_ETH
+int cpu_eth_init(bd_t *bis)
+{
+       lpc32xx_eth_initialize(bis);
+       return 0;
+}
+#endif