ARM: at91: collect SoC sources into mach-at91

[oweals/u-boot.git] / arch / arm / cpu / arm720t / tegra30 / cpu.c

diff --git a/arch/arm/cpu/arm720t/tegra30/cpu.c b/arch/arm/cpu/arm720t/tegra30/cpu.c
index dedcdd9b08ce4ca58b8df41fa88eb2c9ea6c0b81..9003902e3ff704c6244ff1cc0e804fd577c3ad1b 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra30/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra30/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2010-2014, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config)
        writel(config, &reg->cnfg);
 }
 
+#define TPS62366A_I2C_ADDR             0xC0
+#define TPS62366A_SET1_REG             0x01
+#define TPS62366A_SET1_DATA            (0x4600 | TPS62366A_SET1_REG)
+
+#define TPS62361B_I2C_ADDR             0xC0
+#define TPS62361B_SET3_REG             0x03
+#define TPS62361B_SET3_DATA            (0x4600 | TPS62361B_SET3_REG)
+
 #define TPS65911_I2C_ADDR              0x5A
 #define TPS65911_VDDCTRL_OP_REG                0x28
 #define TPS65911_VDDCTRL_SR_REG                0x27
-#define TPS65911_VDDCTRL_OP_DATA       (0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_OP_DATA       (0x2400 | TPS65911_VDDCTRL_OP_REG)
 #define TPS65911_VDDCTRL_SR_DATA       (0x0100 | TPS65911_VDDCTRL_SR_REG)
 #define I2C_SEND_2_BYTES               0x0A02
 
@@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void)
        reg |= CPUPWRREQ_OE;
        writel(reg, &pmc->pmc_cntrl);
 
+       /* Set VDD_CORE to 1.200V. */
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+       tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
+#endif
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+       tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
+#endif
+       udelay(1000);
+
        /*
         * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-        * First set VDD to 1.4V, then enable the VDD regulator.
+        * First set VDD to 1.0125V, then enable the VDD regulator.
         */
        tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
        tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
@@ -84,18 +103,6 @@ void t30_init_clocks(void)
        /* Set active CPU cluster to G */
        clrbits_le32(flow->cluster_control, 1 << 0);
 
-       /*
-        * Switch system clock to PLLP_OUT4 (108 MHz), AVP will now run
-        * at 108 MHz. This is glitch free as only the source is changed, no
-        * special precaution needed.
-        */
-       val = (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
-               (SCLK_SOURCE_PLLP_OUT4 << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
-               (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
-       writel(val, &clkrst->crc_sclk_brst_pol);
-
        writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
 
        val = (0 << CLK_SYS_RATE_HCLK_DISABLE_SHIFT) |
@@ -110,8 +117,8 @@ void t30_init_clocks(void)
        reset_set_enable(PERIPH_ID_MSELECT, 1);
        clock_set_enable(PERIPH_ID_MSELECT, 1);
 
-       /* Switch MSELECT clock to PLLP (00) */
-       clock_ll_set_source(PERIPH_ID_MSELECT, 0);
+       /* Switch MSELECT clock to PLLP (00) and use a divisor of 2 */
+       clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0, 2);
 
        /*
         * Our high-level clock routines are not available prior to