ARM: at91: collect SoC sources into mach-at91
[oweals/u-boot.git] / arch / arm / cpu / arm720t / tegra30 / cpu.c
index 85a945bc7918581ae8ee722f76eabdbbc59ca84f..9003902e3ff704c6244ff1cc0e804fd577c3ad1b 100644 (file)
@@ -41,10 +41,18 @@ void tegra_i2c_ll_write_data(uint data, uint config)
        writel(config, &reg->cnfg);
 }
 
+#define TPS62366A_I2C_ADDR             0xC0
+#define TPS62366A_SET1_REG             0x01
+#define TPS62366A_SET1_DATA            (0x4600 | TPS62366A_SET1_REG)
+
+#define TPS62361B_I2C_ADDR             0xC0
+#define TPS62361B_SET3_REG             0x03
+#define TPS62361B_SET3_DATA            (0x4600 | TPS62361B_SET3_REG)
+
 #define TPS65911_I2C_ADDR              0x5A
 #define TPS65911_VDDCTRL_OP_REG                0x28
 #define TPS65911_VDDCTRL_SR_REG                0x27
-#define TPS65911_VDDCTRL_OP_DATA       (0x2300 | TPS65911_VDDCTRL_OP_REG)
+#define TPS65911_VDDCTRL_OP_DATA       (0x2400 | TPS65911_VDDCTRL_OP_REG)
 #define TPS65911_VDDCTRL_SR_DATA       (0x0100 | TPS65911_VDDCTRL_SR_REG)
 #define I2C_SEND_2_BYTES               0x0A02
 
@@ -58,9 +66,20 @@ static void enable_cpu_power_rail(void)
        reg |= CPUPWRREQ_OE;
        writel(reg, &pmc->pmc_cntrl);
 
+       /* Set VDD_CORE to 1.200V. */
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
+       tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
+#endif
+#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
+       tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
+       tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
+#endif
+       udelay(1000);
+
        /*
         * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
-        * First set VDD to 1.0V, then enable the VDD regulator.
+        * First set VDD to 1.0125V, then enable the VDD regulator.
         */
        tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
        tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);