default 64 if SYS_CACHE_SHIFT_6
default 32 if SYS_CACHE_SHIFT_5
+choice
+ prompt "Select the ARM data write cache policy"
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
+ TARGET_BCMNSP || CPU_PXA || RZA1
+ default SYS_ARM_CACHE_WRITEBACK
+
+config SYS_ARM_CACHE_WRITEBACK
+ bool "Write-back (WB)"
+ help
+ A write updates the cache only and marks the cache line as dirty.
+ External memory is updated only when the line is evicted or explicitly
+ cleaned.
+
+config SYS_ARM_CACHE_WRITETHROUGH
+ bool "Write-through (WT)"
+ help
+ A write updates both the cache and the external memory system.
+ This does not mark the cache line as dirty.
+
+config SYS_ARM_CACHE_WRITEALLOC
+ bool "Write allocation (WA)"
+ help
+ A cache line is allocated on a write miss. This means that executing a
+ store instruction on the processor might cause a burst read to occur.
+ There is a linefill to obtain the data for the cache line, before the
+ write is performed.
+endchoice
+
config ARCH_CPU_INIT
bool "Enable ARCH_CPU_INIT"
help
help
Support for TI's DaVinci platform.
-config KIRKWOOD
+config ARCH_KIRKWOOD
bool "Marvell Kirkwood"
select ARCH_MISC_INIT
select BOARD_EARLY_INIT_F
select CPU_ARM926EJS
select SUPPORT_SPL
-config ORION5X
+config ARCH_ORION5X
bool "Marvell Orion"
select CPU_ARM926EJS
select CLK
select CLK_OWL
select OF_CONTROL
- select CONFIG_SYS_RELOC_GD_ENV_ADDR
+ select SYS_RELOC_GD_ENV_ADDR
imply CMD_DM
config ARCH_QEMU
imply MP
imply DM_USB_GADGET
-config TEGRA
+config ARCH_TEGRA
bool "NVIDIA Tegra"
imply DISTRO_DEFAULTS
imply FAT_WRITE
bool "Support Versatile Express Juno Development Platform"
select ARM64
select PL01X_SERIAL
+ select DM
+ select OF_CONTROL
+ select OF_BOARD
+ select CLK
+ select DM_SERIAL
+ select ARM_PSCI_FW
+ select PSCI_RESET
+ select DM
+ select BLK
+ select USB
+ select DM_USB
config TARGET_LS2080A_EMU
bool "Support ls2080a_emu"
bool "Socionext UniPhier SoCs"
select BOARD_LATE_INIT
select DM
+ select DM_ETH
select DM_GPIO
select DM_I2C
select DM_MMC
Support for UniPhier SoC family developed by Socionext Inc.
(formerly, System LSI Business Division of Panasonic Corporation)
-config STM32
+config ARCH_STM32
bool "Support STMicroelectronics STM32 MCU with cortex M"
select CPU_V7M
select DM
source "arch/arm/mach-kirkwood/Kconfig"
-source "arch/arm/cpu/arm926ejs/lpc32xx/Kconfig"
+source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-mvebu/Kconfig"