Merge tag 'u-boot-atmel-fixes-2020.07-a' of https://gitlab.denx.de/u-boot/custodians...

[oweals/u-boot.git] / arch / arc / dts / axs10x_mb.dtsi

diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi
index dfc03810ca0d75e46f9ca0849a25a61183cc3503..33b05934387a268b649acba912f2269565c344f4 100644 (file)
--- a/arch/arc/dts/axs10x_mb.dtsi
+++ b/arch/arc/dts/axs10x_mb.dtsi
@@ -31,10 +31,29 @@
                                #clock-cells = <0>;
                                u-boot,dm-pre-reloc;
                        };
+
+                       mmcclk_ciu: mmcclk-ciu {
+                               compatible = "fixed-clock";
+                               /*
+                                * DW sdio controller has external ciu clock divider
+                                * controlled via register in SDIO IP. It divides
+                                * sdio_ref_clk (which comes from CGU) by 16 for
+                                * default. So default mmcclk clock (which comes
+                                * to sdk_in) is 25000000 Hz.
+                                */
+                               clock-frequency = <25000000>;
+                               #clock-cells = <0>;
+                       };
+
+                       mmcclk_biu: mmcclk-biu {
+                               compatible = "fixed-clock";
+                               clock-frequency = <50000000>;
+                               #clock-cells = <0>;
+                       };
                };
 
                ethernet@18000 {
-                       compatible = "altr,socfpga-stmmac";
+                       compatible = "snps,arc-dwmac-3.70a";
                        reg = < 0x18000 0x2000 >;
                        phy-mode = "gmii";
                        snps,pbl = < 32 >;
@@ -43,16 +62,25 @@
                        max-speed = <100>;
                };
 
-               ehci@0x40000 {
+               ehci@40000 {
                        compatible = "generic-ehci";
                        reg = < 0x40000 0x100 >;
                };
 
-               ohci@0x60000 {
+               ohci@60000 {
                        compatible = "generic-ohci";
                        reg = < 0x60000 0x100 >;
                };
 
+               mmc: mmc@15000 {
+                       compatible = "snps,dw-mshc";
+                       reg = <0x15000 0x400>;
+                       bus-width = <4>;
+                       clocks = <&mmcclk_biu>, <&mmcclk_ciu>;
+                       clock-names = "biu", "ciu";
+                       max-frequency = <25000000>;
+               };
+
                uart0: serial0@22000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x22000 0x100>;
@@ -71,7 +99,7 @@
                        clock-names = "spi_clk";
                        cs-gpio = <&cs_gpio 0>;
                        spi_flash@0 {
-                               compatible = "spi-flash";
+                               compatible = "jedec,spi-nor";
                                reg = <0>;
                                spi-max-frequency = <4000000>;
                        };