x86: Update SPL for coreboot

[oweals/u-boot.git] / README

diff --git a/README b/README
index 841412bacc676e82ee42185f47568f2330ff2f83..083485067654c319b7f7b84227ae23c689467b1d 100644 (file)
--- a/README
+++ b/README
@@ -1632,16 +1632,6 @@ The following options need to be configured:
                  - activate this driver with CONFIG_SYS_I2C_RCAR
                  - This driver adds 4 i2c buses
 
-                 - CONFIG_SYS_RCAR_I2C0_BASE for setting the register channel 0
-                 - CONFIG_SYS_RCAR_I2C0_SPEED for for the speed channel 0
-                 - CONFIG_SYS_RCAR_I2C1_BASE for setting the register channel 1
-                 - CONFIG_SYS_RCAR_I2C1_SPEED for for the speed channel 1
-                 - CONFIG_SYS_RCAR_I2C2_BASE for setting the register channel 2
-                 - CONFIG_SYS_RCAR_I2C2_SPEED for for the speed channel 2
-                 - CONFIG_SYS_RCAR_I2C3_BASE for setting the register channel 3
-                 - CONFIG_SYS_RCAR_I2C3_SPEED for for the speed channel 3
-                 - CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS for number of i2c buses
-
                - drivers/i2c/sh_i2c.c:
                  - activate this driver with CONFIG_SYS_I2C_SH
                  - This driver adds from 2 to 5 i2c buses