// SPDX-License-Identifier: GPL-2.0+ OR X11 /* * T2080/T2081 Silicon/SoC Device Tree Source (pre include) * * Copyright 2013 Freescale Semiconductor Inc. * Copyright 2018 NXP */ /dts-v1/; /include/ "e6500_power_isa.dtsi" / { #address-cells = <2>; #size-cells = <2>; interrupt-parent = <&mpic>; cpus { #address-cells = <1>; #size-cells = <0>; cpu0: PowerPC,e6500@0 { device_type = "cpu"; reg = <0 1>; fsl,portid-mapping = <0x80000000>; }; cpu1: PowerPC,e6500@2 { device_type = "cpu"; reg = <2 3>; fsl,portid-mapping = <0x80000000>; }; cpu2: PowerPC,e6500@4 { device_type = "cpu"; reg = <4 5>; fsl,portid-mapping = <0x80000000>; }; cpu3: PowerPC,e6500@6 { device_type = "cpu"; reg = <6 7>; fsl,portid-mapping = <0x80000000>; }; }; soc: soc@ffe000000 { ranges = <0x00000000 0xf 0xfe000000 0x1000000>; reg = <0xf 0xfe000000 0 0x00001000>; #address-cells = <1>; #size-cells = <1>; device_type = "soc"; compatible = "simple-bus"; mpic: pic@40000 { interrupt-controller; #address-cells = <0>; #interrupt-cells = <4>; reg = <0x40000 0x40000>; compatible = "fsl,mpic"; device_type = "open-pic"; clock-frequency = <0x0>; }; esdhc: esdhc@114000 { compatible = "fsl,esdhc"; reg = <0x114000 0x1000>; interrupts = <48 2 0 0>; clock-frequency = <0>; sdhci,auto-cmd12; bus-width = <4>; voltage-ranges = <1800 1800 3300 3300>; }; usb0: usb@210000 { compatible = "fsl-usb2-mph"; reg = <0x210000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <44 0x2 0 0>; phy_type = "utmi"; }; usb1: usb@211000 { compatible = "fsl-usb2-dr"; reg = <0x211000 0x1000>; #address-cells = <1>; #size-cells = <0>; interrupts = <45 0x2 0 0>; dr_mode = "host"; phy_type = "utmi"; }; sata0: sata@220000 { compatible = "fsl,pq-sata-v2"; reg = <0x220000 0x1000>; interrupts = <68 0x2 0 0>; sata-number = <0x0>; sata-fpdma = <0x0>; }; sata1: sata@221000 { compatible = "fsl,pq-sata-v2"; reg = <0x221000 0x1000>; interrupts = <69 0x2 0 0>; sata-number = <0x0>; sata-fpdma = <0x0>; }; }; };