// SPDX-License-Identifier: GPL-2.0 /* * Device Tree Source for the r8a77965 SoC * * Copyright (C) 2018 Jacopo Mondi * * Based on r8a7796.dtsi * Copyright (C) 2016 Renesas Electronics Corp. */ #include #include #define CPG_AUDIO_CLK_I 10 / { compatible = "renesas,r8a77965"; #address-cells = <2>; #size-cells = <2>; aliases { i2c7 = &i2c_dvfs; }; psci { compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; cpus { #address-cells = <1>; #size-cells = <0>; a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; device_type = "cpu"; power-domains = <&sysc 0>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; a57_1: cpu@1 { compatible = "arm,cortex-a57","arm,armv8"; reg = <0x1>; device_type = "cpu"; power-domains = <&sysc 1>; next-level-cache = <&L2_CA57>; enable-method = "psci"; }; L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc 12>; cache-unified; cache-level = <2>; }; }; extal_clk: extal { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; extalr_clk: extalr { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by the board */ clock-frequency = <0>; }; /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. * Boards that provide audio clocks should override them. */ audio_clk_a: audio_clk_a { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; audio_clk_b: audio_clk_b { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; audio_clk_c: audio_clk_c { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External SCIF clock - to be overridden by boards that provide it */ scif_clk: scif { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External PCIe clock - can be overridden by the board */ pcie_bus_clk: pcie_bus { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; /* External USB clocks - can be overridden by the board */ usb3s0_clk: usb3s0 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; usb_extal_clk: usb_extal { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <0>; }; timer { compatible = "arm,armv8-timer"; interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; pmu_a57 { compatible = "arm,cortex-a57-pmu"; interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; interrupt-affinity = <&a57_0>, <&a57_1>; }; soc: soc { compatible = "simple-bus"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; ranges; gic: interrupt-controller@f1010000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; reg = <0x0 0xf1010000 0 0x1000>, <0x0 0xf1020000 0 0x20000>, <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc 32>; resets = <&cpg 408>; }; pfc: pin-controller@e6060000 { compatible = "renesas,pfc-r8a77965"; reg = <0 0xe6060000 0 0x50c>; }; cpg: clock-controller@e6150000 { compatible = "renesas,r8a77965-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>, <&extalr_clk>; clock-names = "extal", "extalr"; #clock-cells = <2>; #power-domain-cells = <0>; #reset-cells = <1>; }; rst: reset-controller@e6160000 { compatible = "renesas,r8a77965-rst"; reg = <0 0xe6160000 0 0x0200>; }; prr: chipid@fff00044 { compatible = "renesas,prr"; reg = <0 0xfff00044 0 4>; }; sysc: system-controller@e6180000 { compatible = "renesas,r8a77965-sysc"; reg = <0 0xe6180000 0 0x0400>; #power-domain-cells = <1>; }; gpio0: gpio@e6050000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6050000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 0 16>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc 32>; resets = <&cpg 912>; }; gpio1: gpio@e6051000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6051000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 32 29>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc 32>; resets = <&cpg 911>; }; gpio2: gpio@e6052000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6052000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 64 15>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc 32>; resets = <&cpg 910>; }; gpio3: gpio@e6053000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6053000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 96 16>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc 32>; resets = <&cpg 909>; }; gpio4: gpio@e6054000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6054000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 128 18>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc 32>; resets = <&cpg 908>; }; gpio5: gpio@e6055000 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055000 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 160 26>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc 32>; resets = <&cpg 907>; }; gpio6: gpio@e6055400 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055400 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 906>; power-domains = <&sysc 32>; resets = <&cpg 906>; }; gpio7: gpio@e6055800 { compatible = "renesas,gpio-r8a77965", "renesas,rcar-gen3-gpio"; reg = <0 0xe6055800 0 0x50>; interrupts = ; #gpio-cells = <2>; gpio-controller; gpio-ranges = <&pfc 0 224 4>; #interrupt-cells = <2>; interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc 32>; resets = <&cpg 905>; }; intc_ex: interrupt-controller@e61c0000 { compatible = "renesas,intc-ex-r8a77965", "renesas,irqc"; #interrupt-cells = <2>; interrupt-controller; reg = <0 0xe61c0000 0 0x200>; interrupts = ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc 32>; resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; reg = <0 0xe6700000 0 0x10000>; interrupts = ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc 32>; resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <16>; }; dmac1: dma-controller@e7300000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; reg = <0 0xe7300000 0 0x10000>; interrupts = ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc 32>; resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <16>; }; dmac2: dma-controller@e7310000 { compatible = "renesas,dmac-r8a77965", "renesas,rcar-dmac"; reg = <0 0xe7310000 0 0x10000>; interrupts = ; interrupt-names = "error", "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15"; clocks = <&cpg CPG_MOD 217>; clock-names = "fck"; power-domains = <&sysc 32>; resets = <&cpg 217>; #dma-cells = <1>; dma-channels = <16>; }; scif0: serial@e6e60000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 207>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x51>, <&dmac1 0x50>, <&dmac2 0x51>, <&dmac2 0x50>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 207>; status = "disabled"; }; scif1: serial@e6e68000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 206>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x53>, <&dmac1 0x52>, <&dmac2 0x53>, <&dmac2 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 206>; status = "disabled"; }; scif2: serial@e6e88000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6e88000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; power-domains = <&sysc 32>; resets = <&cpg 310>; status = "disabled"; }; scif3: serial@e6c50000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6c50000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 204>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x57>, <&dmac0 0x56>; dma-names = "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 204>; status = "disabled"; }; scif4: serial@e6c40000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6c40000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 203>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x59>, <&dmac0 0x58>; dma-names = "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 203>; status = "disabled"; }; scif5: serial@e6f30000 { compatible = "renesas,scif-r8a77965", "renesas,rcar-gen3-scif", "renesas,scif"; reg = <0 0xe6f30000 0 64>; interrupts = ; clocks = <&cpg CPG_MOD 202>, <&cpg CPG_CORE 20>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, <&dmac2 0x5b>, <&dmac2 0x5a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc 32>; resets = <&cpg 202>; status = "disabled"; }; avb: ethernet@e6800000 { compatible = "renesas,etheravb-r8a77965", "renesas,etheravb-rcar-gen3"; reg = <0 0xe6800000 0 0x800>, <0 0xe6a00000 0 0x10000>; interrupts = , , , , , , , , , , , , , , , , , , , , , , , , ; interrupt-names = "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14", "ch15", "ch16", "ch17", "ch18", "ch19", "ch20", "ch21", "ch22", "ch23", "ch24"; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc 32>; resets = <&cpg 812>; phy-mode = "rgmii"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; }; csi20: csi2@fea80000 { reg = <0 0xfea80000 0 0x10000>; /* placeholder */ ports { #address-cells = <1>; #size-cells = <0>; }; }; csi40: csi2@feaa0000 { reg = <0 0xfeaa0000 0 0x10000>; /* placeholder */ ports { #address-cells = <1>; #size-cells = <0>; }; }; vin0: video@e6ef0000 { reg = <0 0xe6ef0000 0 0x1000>; /* placeholder */ }; vin1: video@e6ef1000 { reg = <0 0xe6ef1000 0 0x1000>; /* placeholder */ }; vin2: video@e6ef2000 { reg = <0 0xe6ef2000 0 0x1000>; /* placeholder */ }; vin3: video@e6ef3000 { reg = <0 0xe6ef3000 0 0x1000>; /* placeholder */ }; vin4: video@e6ef4000 { reg = <0 0xe6ef4000 0 0x1000>; /* placeholder */ }; vin5: video@e6ef5000 { reg = <0 0xe6ef5000 0 0x1000>; /* placeholder */ }; vin6: video@e6ef6000 { reg = <0 0xe6ef6000 0 0x1000>; /* placeholder */ }; vin7: video@e6ef7000 { reg = <0 0xe6ef7000 0 0x1000>; /* placeholder */ }; ohci0: usb@ee080000 { reg = <0 0xee080000 0 0x100>; /* placeholder */ }; ehci0: usb@ee080100 { reg = <0 0xee080100 0 0x100>; /* placeholder */ }; usb2_phy0: usb-phy@ee080200 { reg = <0 0xee080200 0 0x700>; /* placeholder */ }; usb2_phy1: usb-phy@ee0a0200 { reg = <0 0xee0a0200 0 0x700>; /* placeholder */ }; ohci1: usb@ee0a0000 { reg = <0 0xee0a0000 0 0x100>; /* placeholder */ }; ehci1: usb@ee0a0100 { reg = <0 0xee0a0100 0 0x100>; /* placeholder */ }; i2c0: i2c@e6500000 { reg = <0 0xe6500000 0 0x40>; /* placeholder */ }; i2c1: i2c@e6508000 { reg = <0 0xe6508000 0 0x40>; /* placeholder */ }; i2c2: i2c@e6510000 { #address-cells = <1>; #size-cells = <0>; reg = <0 0xe6510000 0 0x40>; /* placeholder */ }; i2c3: i2c@e66d0000 { reg = <0 0xe66d0000 0 0x40>; /* placeholder */ }; i2c4: i2c@e66d8000 { #address-cells = <1>; #size-cells = <0>; reg = <0 0xe66d8000 0 0x40>; /* placeholder */ }; i2c5: i2c@e66e0000 { reg = <0 0xe66e0000 0 0x40>; /* placeholder */ }; i2c6: i2c@e66e8000 { reg = <0 0xe66e8000 0 0x40>; /* placeholder */ }; i2c_dvfs: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a77965", "renesas,rcar-gen3-iic", "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; clocks = <&cpg CPG_MOD 926>; power-domains = <&sysc 32>; resets = <&cpg 926>; dmas = <&dmac0 0x11>, <&dmac0 0x10>; dma-names = "tx", "rx"; status = "disabled"; }; pwm0: pwm@e6e30000 { reg = <0 0xe6e30000 0 8>; /* placeholder */ }; pwm1: pwm@e6e31000 { reg = <0 0xe6e31000 0 8>; #pwm-cells = <2>; /* placeholder */ }; pwm2: pwm@e6e32000 { reg = <0 0xe6e32000 0 8>; /* placeholder */ }; pwm3: pwm@e6e33000 { reg = <0 0xe6e33000 0 8>; /* placeholder */ }; pwm4: pwm@e6e34000 { reg = <0 0xe6e34000 0 8>; /* placeholder */ }; pwm5: pwm@e6e35000 { reg = <0 0xe6e35000 0 8>; /* placeholder */ }; pwm6: pwm@e6e36000 { reg = <0 0xe6e36000 0 8>; /* placeholder */ }; du: display@feb00000 { reg = <0 0xfeb00000 0 0x80000>, <0 0xfeb90000 0 0x14>; /* placeholder */ ports { #address-cells = <1>; #size-cells = <0>; port@0 { reg = <0>; du_out_rgb: endpoint { }; }; port@1 { reg = <1>; du_out_hdmi0: endpoint { }; }; port@2 { reg = <2>; du_out_lvds0: endpoint { }; }; }; }; hsusb: usb@e6590000 { reg = <0 0xe6590000 0 0x100>; /* placeholder */ }; pciec0: pcie@fe000000 { reg = <0 0xfe000000 0 0x80000>; /* placeholder */ }; pciec1: pcie@ee800000 { reg = <0 0xee800000 0 0x80000>; /* placeholder */ }; rcar_sound: sound@ec500000 { reg = <0 0xec500000 0 0x1000>, /* SCU */ <0 0xec5a0000 0 0x100>, /* ADG */ <0 0xec540000 0 0x1000>, /* SSIU */ <0 0xec541000 0 0x280>, /* SSI */ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ /* placeholder */ rcar_sound,dvc { dvc0: dvc-0 { }; dvc1: dvc-1 { }; }; rcar_sound,src { src0: src-0 { }; src1: src-1 { }; }; rcar_sound,ssi { ssi0: ssi-0 { }; ssi1: ssi-1 { }; }; }; sdhi0: sd@ee100000 { reg = <0 0xee100000 0 0x2000>; /* placeholder */ }; sdhi1: sd@ee120000 { reg = <0 0xee120000 0 0x2000>; /* placeholder */ }; sdhi2: sd@ee140000 { reg = <0 0xee140000 0 0x2000>; /* placeholder */ }; sdhi3: sd@ee160000 { reg = <0 0xee160000 0 0x2000>; /* placeholder */ }; usb3_phy0: usb-phy@e65ee000 { reg = <0 0xe65ee000 0 0x90>; #phy-cells = <0>; /* placeholder */ }; usb3_peri0: usb@ee020000 { reg = <0 0xee020000 0 0x400>; /* placeholder */ }; xhci0: usb@ee000000 { reg = <0 0xee000000 0 0xc00>; /* placeholder */ }; wdt0: watchdog@e6020000 { reg = <0 0xe6020000 0 0x0c>; /* placeholder */ }; }; };