1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/sci/sci.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/arch-imx/cpu.h>
13 #include <asm/armv8/cpu.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 struct cpu_imx_platdata {
26 const char *get_imx8_type(u32 imxtype)
30 case MXC_CPU_IMX8QXP_A0:
39 const char *get_imx8_rev(u32 rev)
53 const char *get_core_name(struct udevice *dev)
55 if (!device_is_compatible(dev, "arm,cortex-a35"))
57 else if (!device_is_compatible(dev, "arm,cortex-a53"))
59 else if (!device_is_compatible(dev, "arm,cortex-a72"))
65 #if IS_ENABLED(CONFIG_IMX_SCU_THERMAL)
66 static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
68 struct udevice *thermal_dev;
71 if (!strcmp(plat->name, "A72"))
72 ret = uclass_get_device(UCLASS_THERMAL, 1, &thermal_dev);
74 ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
77 ret = thermal_get_temp(thermal_dev, &cpu_tmp);
87 static int cpu_imx_get_temp(struct cpu_imx_platdata *plat)
93 int cpu_imx_get_desc(struct udevice *dev, char *buf, int size)
95 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
101 ret = snprintf(buf, size, "NXP i.MX8%s Rev%s %s at %u MHz",
102 plat->type, plat->rev, plat->name, plat->freq_mhz);
104 if (IS_ENABLED(CONFIG_IMX_SCU_THERMAL)) {
105 temp = cpu_imx_get_temp(plat);
108 if (temp != 0xdeadbeef)
109 ret = snprintf(buf, size, " at %dC", temp);
111 ret = snprintf(buf, size, " - invalid sensor data");
114 snprintf(buf + ret, size - ret, "\n");
119 static int cpu_imx_get_info(struct udevice *dev, struct cpu_info *info)
121 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
123 info->cpu_freq = plat->freq_mhz * 1000;
124 info->features = BIT(CPU_FEAT_L1_CACHE) | BIT(CPU_FEAT_MMU);
128 static int cpu_imx_get_count(struct udevice *dev)
133 ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
134 const char *device_type;
136 if (!ofnode_is_available(node))
139 device_type = ofnode_read_string(node, "device_type");
143 if (!strcmp(device_type, "cpu"))
150 static int cpu_imx_get_vendor(struct udevice *dev, char *buf, int size)
152 snprintf(buf, size, "NXP");
156 static int cpu_imx_is_current(struct udevice *dev)
158 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
160 if (plat->mpidr == (read_mpidr() & 0xffff))
166 static const struct cpu_ops cpu_imx8_ops = {
167 .get_desc = cpu_imx_get_desc,
168 .get_info = cpu_imx_get_info,
169 .get_count = cpu_imx_get_count,
170 .get_vendor = cpu_imx_get_vendor,
171 .is_current = cpu_imx_is_current,
174 static const struct udevice_id cpu_imx8_ids[] = {
175 { .compatible = "arm,cortex-a35" },
176 { .compatible = "arm,cortex-a53" },
177 { .compatible = "arm,cortex-a72" },
181 static ulong imx8_get_cpu_rate(struct udevice *dev)
186 if (!device_is_compatible(dev, "arm,cortex-a35"))
188 else if (!device_is_compatible(dev, "arm,cortex-a53"))
190 else if (!device_is_compatible(dev, "arm,cortex-a72"))
195 ret = sc_pm_get_clock_rate(-1, type, SC_PM_CLK_CPU,
196 (sc_pm_clock_rate_t *)&rate);
198 printf("Could not read CPU frequency: %d\n", ret);
205 static int imx8_cpu_probe(struct udevice *dev)
207 struct cpu_imx_platdata *plat = dev_get_platdata(dev);
210 cpurev = get_cpu_rev();
211 plat->cpurev = cpurev;
212 plat->name = get_core_name(dev);
213 plat->rev = get_imx8_rev(cpurev & 0xFFF);
214 plat->type = get_imx8_type((cpurev & 0xFF000) >> 12);
215 plat->freq_mhz = imx8_get_cpu_rate(dev) / 1000000;
216 plat->mpidr = dev_read_addr(dev);
217 if (plat->mpidr == FDT_ADDR_T_NONE) {
218 printf("%s: Failed to get CPU reg property\n", __func__);
225 U_BOOT_DRIVER(cpu_imx8_drv) = {
228 .of_match = cpu_imx8_ids,
229 .ops = &cpu_imx8_ops,
230 .probe = imx8_cpu_probe,
231 .platdata_auto_alloc_size = sizeof(struct cpu_imx_platdata),
232 .flags = DM_FLAG_PRE_RELOC,