board/firefly/firefly-rk3308/roc_cc_rk3308.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2019 Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <common.h>
   7 #include <adc.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/grf_rk3308.h>
  10 #include <asm/arch-rockchip/hardware.h>
  11 #include <linux/bitops.h>
  12
  13 #if defined(CONFIG_DEBUG_UART)
  14 #define GRF_BASE        0xff000000
  15
  16 enum {
  17         GPIO1C7_SHIFT           = 8,
  18         GPIO1C7_MASK            = GENMASK(11, 8),
  19         GPIO1C7_GPIO            = 0,
  20         GPIO1C7_UART1_RTSN,
  21         GPIO1C7_UART2_TX_M0,
  22         GPIO1C7_SPI2_MOSI,
  23         GPIO1C7_JTAG_TMS,
  24
  25         GPIO1C6_SHIFT           = 4,
  26         GPIO1C6_MASK            = GENMASK(7, 4),
  27         GPIO1C6_GPIO            = 0,
  28         GPIO1C6_UART1_CTSN,
  29         GPIO1C6_UART2_RX_M0,
  30         GPIO1C6_SPI2_MISO,
  31         GPIO1C6_JTAG_TCLK,
  32
  33         GPIO4D3_SHIFT           = 6,
  34         GPIO4D3_MASK            = GENMASK(7, 6),
  35         GPIO4D3_GPIO            = 0,
  36         GPIO4D3_SDMMC_D3,
  37         GPIO4D3_UART2_TX_M1,
  38
  39         GPIO4D2_SHIFT           = 4,
  40         GPIO4D2_MASK            = GENMASK(5, 4),
  41         GPIO4D2_GPIO            = 0,
  42         GPIO4D2_SDMMC_D2,
  43         GPIO4D2_UART2_RX_M1,
  44
  45         UART2_IO_SEL_SHIFT      = 2,
  46         UART2_IO_SEL_MASK       = GENMASK(3, 2),
  47         UART2_IO_SEL_M0         = 0,
  48         UART2_IO_SEL_M1,
  49         UART2_IO_SEL_USB,
  50 };
  51
  52 void board_debug_uart_init(void)
  53 {
  54         static struct rk3308_grf * const grf = (void *)GRF_BASE;
  55
  56         /* Enable early UART2 channel m0 on the rk3308 */
  57         rk_clrsetreg(&grf->soc_con5, UART2_IO_SEL_MASK,
  58                      UART2_IO_SEL_M0 << UART2_IO_SEL_SHIFT);
  59         rk_clrsetreg(&grf->gpio1ch_iomux,
  60                      GPIO1C6_MASK | GPIO1C7_MASK,
  61                      GPIO1C6_UART2_RX_M0 << GPIO1C6_SHIFT |
  62                      GPIO1C7_UART2_TX_M0 << GPIO1C7_SHIFT);
  63 }
  64 #endif
  65
  66 #define KEY_DOWN_MIN_VAL        0
  67 #define KEY_DOWN_MAX_VAL        30
  68
  69 int rockchip_dnl_key_pressed(void)
  70 {
  71         unsigned int val;
  72
  73         if (adc_channel_single_shot("saradc", 1, &val)) {
  74                 printf("%s read adc key val failed\n", __func__);
  75                 return false;
  76         }
  77
  78         if (val >= KEY_DOWN_MIN_VAL && val <= KEY_DOWN_MAX_VAL)
  79                 return true;
  80         else
  81                 return false;
  82 }