board/el/el6x/el6x.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) Stefano Babic <sbabic@denx.de>
   4  *
   5  * Based on other i.MX6 boards
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <net.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <env.h>
  16 #include <linux/delay.h>
  17 #include <linux/errno.h>
  18 #include <asm/gpio.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <asm/mach-imx/iomux-v3.h>
  21 #include <asm/mach-imx/boot_mode.h>
  22 #include <asm/mach-imx/video.h>
  23 #include <mmc.h>
  24 #include <fsl_esdhc_imx.h>
  25 #include <miiphy.h>
  26 #include <netdev.h>
  27 #include <asm/arch/mxc_hdmi.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/io.h>
  30 #include <asm/arch/sys_proto.h>
  31 #include <i2c.h>
  32 #include <input.h>
  33 #include <power/pmic.h>
  34 #include <power/pfuze100_pmic.h>
  35 #include <asm/arch/mx6-ddr.h>
  36
  37 DECLARE_GLOBAL_DATA_PTR;
  38
  39 #define OPEN_PAD_CTRL  (PAD_CTL_ODE  | PAD_CTL_DSE_DISABLE | (0 << 12))
  40
  41 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  42         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  43         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  44
  45 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  46         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  47         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  48
  49 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  50         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  51
  52 #define ENET_PAD_CTRL_PD  (PAD_CTL_PUS_100K_DOWN |              \
  53         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL_CLK  ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
  56         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  57
  58 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
  59         PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
  60
  61 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  62         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  63         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  64
  65 #define I2C_PMIC        1
  66
  67 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  68
  69 #define ETH_PHY_RESET   IMX_GPIO_NR(2, 4)
  70
  71 int dram_init(void)
  72 {
  73         gd->ram_size = imx_ddr_size();
  74
  75         return 0;
  76 }
  77
  78 iomux_v3_cfg_t const uart2_pads[] = {
  79         MX6_PAD_SD3_DAT5__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  80         MX6_PAD_SD3_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  81 };
  82
  83 static void setup_iomux_uart(void)
  84 {
  85         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  86 }
  87
  88 #ifdef CONFIG_TARGET_ZC5202
  89 iomux_v3_cfg_t const enet_pads[] = {
  90         MX6_PAD_GPIO_18__ENET_RX_CLK            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  91         MX6_PAD_ENET_RXD0__ENET_RX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  92         MX6_PAD_ENET_RXD1__ENET_RX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  93         MX6_PAD_KEY_COL2__ENET_RX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  94         MX6_PAD_KEY_COL0__ENET_RX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  95         MX6_PAD_ENET_CRS_DV__ENET_RX_EN         | MUX_PAD_CTRL(ENET_PAD_CTRL),
  96         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
  97         MX6_PAD_ENET_TXD0__ENET_TX_DATA0        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  98         MX6_PAD_ENET_TXD1__ENET_TX_DATA1        | MUX_PAD_CTRL(ENET_PAD_CTRL),
  99         MX6_PAD_GPIO_19__ENET_TX_ER             | MUX_PAD_CTRL(ENET_PAD_CTRL),
 100         MX6_PAD_KEY_ROW2__ENET_TX_DATA2         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 101         MX6_PAD_KEY_ROW0__ENET_TX_DATA3         | MUX_PAD_CTRL(ENET_PAD_CTRL),
 102         MX6_PAD_ENET_TX_EN__ENET_TX_EN          | MUX_PAD_CTRL(ENET_PAD_CTRL),
 103         MX6_PAD_ENET_RX_ER__ENET_RX_ER          | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 104         /* Switch Reset */
 105         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(ENET_PAD_CTRL_PD),
 106         /* Switch Interrupt */
 107         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
 108         /* use CRS and COL pads as GPIOs */
 109         MX6_PAD_KEY_COL3__GPIO4_IO12            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
 110         MX6_PAD_KEY_ROW1__GPIO4_IO09            | MUX_PAD_CTRL(OPEN_PAD_CTRL),
 111
 112 };
 113
 114 #define BOARD_NAME "EL6x-ZC5202"
 115 #else
 116 iomux_v3_cfg_t const enet_pads[] = {
 117         MX6_PAD_ENET_MDIO__ENET_MDIO    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 118         MX6_PAD_ENET_MDC__ENET_MDC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 119         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 120         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 121         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 122         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 123         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 124         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 125         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL_CLK),
 126         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 127         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 128         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 129         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 130         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
 131         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 132         MX6_PAD_NANDF_D4__GPIO2_IO04            | MUX_PAD_CTRL(NO_PAD_CTRL),
 133         MX6_PAD_NANDF_D5__GPIO2_IO05            | MUX_PAD_CTRL(NO_PAD_CTRL),
 134 };
 135 #define BOARD_NAME "EL6x-ZC5601"
 136 #endif
 137
 138 static void setup_iomux_enet(void)
 139 {
 140         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 141
 142 #ifdef CONFIG_TARGET_ZC5202
 143         /* set CRS and COL to input */
 144         gpio_direction_input(IMX_GPIO_NR(4, 9));
 145         gpio_direction_input(IMX_GPIO_NR(4, 12));
 146
 147         /* Reset Switch */
 148         gpio_direction_output(ETH_PHY_RESET , 0);
 149         mdelay(2);
 150         gpio_set_value(ETH_PHY_RESET, 1);
 151 #endif
 152 }
 153
 154 int board_phy_config(struct phy_device *phydev)
 155 {
 156         if (phydev->drv->config)
 157                 phydev->drv->config(phydev);
 158
 159         return 0;
 160 }
 161
 162 #ifdef CONFIG_MXC_SPI
 163 #ifdef CONFIG_TARGET_ZC5202
 164 iomux_v3_cfg_t const ecspi1_pads[] = {
 165         MX6_PAD_DISP0_DAT20__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 166         MX6_PAD_DISP0_DAT21__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 167         MX6_PAD_DISP0_DAT22__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 168         MX6_PAD_DISP0_DAT23__GPIO5_IO17  | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         MX6_PAD_DISP0_DAT15__GPIO5_IO09  | MUX_PAD_CTRL(NO_PAD_CTRL),
 170 };
 171
 172 iomux_v3_cfg_t const ecspi3_pads[] = {
 173         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 174         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 175         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 176         MX6_PAD_DISP0_DAT7__GPIO4_IO28   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 177         MX6_PAD_DISP0_DAT8__GPIO4_IO29   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 178         MX6_PAD_DISP0_DAT9__GPIO4_IO30   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 179         MX6_PAD_DISP0_DAT10__GPIO4_IO31  | MUX_PAD_CTRL(SPI_PAD_CTRL),
 180 };
 181 #endif
 182
 183 iomux_v3_cfg_t const ecspi4_pads[] = {
 184         MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 185         MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 186         MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 187         MX6_PAD_EIM_D20__GPIO3_IO20  | MUX_PAD_CTRL(NO_PAD_CTRL),
 188 };
 189
 190 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 191 {
 192         return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS)
 193                 ? (IMX_GPIO_NR(3, 20)) : -1;
 194 }
 195
 196 static void setup_spi(void)
 197 {
 198 #ifdef CONFIG_TARGET_ZC5202
 199         gpio_request(IMX_GPIO_NR(5, 17), "spi_cs0");
 200         gpio_request(IMX_GPIO_NR(5, 9), "spi_cs1");
 201         gpio_direction_output(IMX_GPIO_NR(5, 17), 1);
 202         gpio_direction_output(IMX_GPIO_NR(5, 9), 1);
 203         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 204 #endif
 205
 206         gpio_request(IMX_GPIO_NR(3, 20), "spi4_cs0");
 207         gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
 208         imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads));
 209
 210         enable_spi_clk(true, 3);
 211 }
 212 #endif
 213
 214 static struct i2c_pads_info i2c_pad_info1 = {
 215         .scl = {
 216                 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | I2C_PAD,
 217                 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | I2C_PAD,
 218                 .gp = IMX_GPIO_NR(2, 30)
 219         },
 220         .sda = {
 221                 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
 222                 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 223                 .gp = IMX_GPIO_NR(4, 13)
 224         }
 225 };
 226
 227 static struct i2c_pads_info i2c_pad_info2 = {
 228         .scl = {
 229                 .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | I2C_PAD,
 230                 .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | I2C_PAD,
 231                 .gp = IMX_GPIO_NR(1, 5)
 232         },
 233         .sda = {
 234                 .i2c_mode = MX6_PAD_GPIO_16__I2C3_SDA | I2C_PAD,
 235                 .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | I2C_PAD,
 236                 .gp = IMX_GPIO_NR(7, 11)
 237         }
 238 };
 239
 240 iomux_v3_cfg_t const usdhc2_pads[] = {
 241         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 242         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 243         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 244         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 245         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 246         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 247         MX6_PAD_GPIO_4__SD2_CD_B        | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 248 };
 249
 250 iomux_v3_cfg_t const usdhc4_pads[] = {
 251         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 252         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 253         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 254         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 255         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 256         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 257         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 258         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 259         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 260         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 261 };
 262
 263 #ifdef CONFIG_FSL_ESDHC_IMX
 264 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 265         {USDHC2_BASE_ADDR},
 266         {USDHC4_BASE_ADDR},
 267 };
 268
 269 #define USDHC2_CD_GPIO  IMX_GPIO_NR(1, 4)
 270
 271 int board_mmc_getcd(struct mmc *mmc)
 272 {
 273         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 274         int ret = 0;
 275
 276         switch (cfg->esdhc_base) {
 277         case USDHC2_BASE_ADDR:
 278                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 279                 break;
 280         case USDHC4_BASE_ADDR:
 281                 ret = 1; /* eMMC/uSDHC4 is always present */
 282                 break;
 283         }
 284
 285         return ret;
 286 }
 287
 288 int board_mmc_init(bd_t *bis)
 289 {
 290 #ifndef CONFIG_SPL_BUILD
 291         int ret;
 292         int i;
 293
 294         /*
 295          * According to the board_mmc_init() the following map is done:
 296          * (U-boot device node)    (Physical Port)
 297          * mmc0                    SD2
 298          * mmc1                    SD3
 299          * mmc2                    eMMC
 300          */
 301         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 302                 switch (i) {
 303                 case 0:
 304                         imx_iomux_v3_setup_multiple_pads(
 305                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 306                         gpio_direction_input(USDHC2_CD_GPIO);
 307                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 308                         break;
 309                 case 1:
 310                         imx_iomux_v3_setup_multiple_pads(
 311                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 312                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 313                         break;
 314                 default:
 315                         printf("Warning: you configured more USDHC controllers"
 316                                "(%d) then supported by the board (%d)\n",
 317                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 318                         return -EINVAL;
 319                 }
 320
 321                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 322                 if (ret)
 323                         return ret;
 324         }
 325
 326         return 0;
 327 #else
 328         struct src *psrc = (struct src *)SRC_BASE_ADDR;
 329         unsigned reg = readl(&psrc->sbmr1) >> 11;
 330
 331         /*
 332          * Upon reading BOOT_CFG register the following map is done:
 333          * Bit 11 and 12 of BOOT_CFG register can determine the current
 334          * mmc port
 335          * 0x1                  SD1
 336          * 0x2                  SD2
 337          * 0x3                  SD4
 338          */
 339
 340         switch (reg & 0x3) {
 341         case 0x1:
 342                 imx_iomux_v3_setup_multiple_pads(
 343                         usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 344                 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
 345                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 346                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 347                 break;
 348         case 0x3:
 349                 imx_iomux_v3_setup_multiple_pads(
 350                         usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 351                 usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
 352                 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 353                 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
 354                 break;
 355         }
 356
 357         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 358 #endif
 359
 360 }
 361 #endif
 362
 363
 364 /*
 365  * Do not overwrite the console
 366  * Use always serial for U-Boot console
 367  */
 368 int overwrite_console(void)
 369 {
 370         return 1;
 371 }
 372
 373 int board_eth_init(bd_t *bis)
 374 {
 375         setup_iomux_enet();
 376         enable_enet_clk(1);
 377
 378         return cpu_eth_init(bis);
 379 }
 380
 381 int board_early_init_f(void)
 382 {
 383
 384         setup_iomux_uart();
 385         setup_spi();
 386
 387         return 0;
 388 }
 389
 390 int board_init(void)
 391 {
 392         /* address of boot parameters */
 393         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 394
 395         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 396         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 397
 398         return 0;
 399 }
 400
 401 int power_init_board(void)
 402 {
 403         struct pmic *p;
 404         int ret;
 405         unsigned int reg;
 406
 407         ret = power_pfuze100_init(I2C_PMIC);
 408         if (ret)
 409                 return ret;
 410
 411         p = pmic_get("PFUZE100");
 412         ret = pmic_probe(p);
 413         if (ret)
 414                 return ret;
 415
 416         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 417         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 418
 419         /* Increase VGEN3 from 2.5 to 2.8V */
 420         pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
 421         reg &= ~LDO_VOL_MASK;
 422         reg |= LDOB_2_80V;
 423         pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
 424
 425         /* Increase VGEN5 from 2.8 to 3V */
 426         pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
 427         reg &= ~LDO_VOL_MASK;
 428         reg |= LDOB_3_00V;
 429         pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
 430
 431         /* Set SW1AB stanby volage to 0.975V */
 432         pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 433         reg &= ~SW1x_STBY_MASK;
 434         reg |= SW1x_0_975V;
 435         pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 436
 437         /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
 438         pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 439         reg &= ~SW1xCONF_DVSSPEED_MASK;
 440         reg |= SW1xCONF_DVSSPEED_4US;
 441         pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 442
 443         /* Set SW1C standby voltage to 0.975V */
 444         pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 445         reg &= ~SW1x_STBY_MASK;
 446         reg |= SW1x_0_975V;
 447         pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 448
 449         /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
 450         pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 451         reg &= ~SW1xCONF_DVSSPEED_MASK;
 452         reg |= SW1xCONF_DVSSPEED_4US;
 453         pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 454
 455         return 0;
 456 }
 457
 458 #ifdef CONFIG_CMD_BMODE
 459 static const struct boot_mode board_boot_modes[] = {
 460         /* 4 bit bus width */
 461         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 462         /* 8 bit bus width */
 463         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 464         {NULL,   0},
 465 };
 466 #endif
 467
 468 int board_late_init(void)
 469 {
 470 #ifdef CONFIG_CMD_BMODE
 471         add_board_boot_modes(board_boot_modes);
 472 #endif
 473
 474         env_set("board_name", BOARD_NAME);
 475         return 0;
 476 }
 477
 478 int checkboard(void)
 479 {
 480         puts("Board: ");
 481         puts(BOARD_NAME "\n");
 482
 483         return 0;
 484 }
 485
 486 #ifdef CONFIG_SPL_BUILD
 487 #include <spl.h>
 488 #include <linux/libfdt.h>
 489
 490 const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
 491         .dram_sdclk_0 =  0x00020030,
 492         .dram_sdclk_1 =  0x00020030,
 493         .dram_cas =  0x00020030,
 494         .dram_ras =  0x00020030,
 495         .dram_reset =  0x00020030,
 496         .dram_sdcke0 =  0x00003000,
 497         .dram_sdcke1 =  0x00003000,
 498         .dram_sdba2 =  0x00000000,
 499         .dram_sdodt0 =  0x00003030,
 500         .dram_sdodt1 =  0x00003030,
 501         .dram_sdqs0 =  0x00000030,
 502         .dram_sdqs1 =  0x00000030,
 503         .dram_sdqs2 =  0x00000030,
 504         .dram_sdqs3 =  0x00000030,
 505         .dram_sdqs4 =  0x00000030,
 506         .dram_sdqs5 =  0x00000030,
 507         .dram_sdqs6 =  0x00000030,
 508         .dram_sdqs7 =  0x00000030,
 509         .dram_dqm0 =  0x00020030,
 510         .dram_dqm1 =  0x00020030,
 511         .dram_dqm2 =  0x00020030,
 512         .dram_dqm3 =  0x00020030,
 513         .dram_dqm4 =  0x00020030,
 514         .dram_dqm5 =  0x00020030,
 515         .dram_dqm6 =  0x00020030,
 516         .dram_dqm7 =  0x00020030,
 517 };
 518
 519 const struct mx6dq_iomux_grp_regs mx6_grp_ioregs = {
 520         .grp_ddr_type =  0x000C0000,
 521         .grp_ddrmode_ctl =  0x00020000,
 522         .grp_ddrpke =  0x00000000,
 523         .grp_addds =  0x00000030,
 524         .grp_ctlds =  0x00000030,
 525         .grp_ddrmode =  0x00020000,
 526         .grp_b0ds =  0x00000030,
 527         .grp_b1ds =  0x00000030,
 528         .grp_b2ds =  0x00000030,
 529         .grp_b3ds =  0x00000030,
 530         .grp_b4ds =  0x00000030,
 531         .grp_b5ds =  0x00000030,
 532         .grp_b6ds =  0x00000030,
 533         .grp_b7ds =  0x00000030,
 534 };
 535
 536 const struct mx6_mmdc_calibration mx6_mmcd_calib = {
 537         .p0_mpwldectrl0 =  0x001F001F,
 538         .p0_mpwldectrl1 =  0x001F001F,
 539         .p1_mpwldectrl0 =  0x00440044,
 540         .p1_mpwldectrl1 =  0x00440044,
 541         .p0_mpdgctrl0 =  0x434B0350,
 542         .p0_mpdgctrl1 =  0x034C0359,
 543         .p1_mpdgctrl0 =  0x434B0350,
 544         .p1_mpdgctrl1 =  0x03650348,
 545         .p0_mprddlctl =  0x4436383B,
 546         .p1_mprddlctl =  0x39393341,
 547         .p0_mpwrdlctl =  0x35373933,
 548         .p1_mpwrdlctl =  0x48254A36,
 549 };
 550
 551 /* MT41K128M16JT-125 */
 552 static struct mx6_ddr3_cfg mem_ddr = {
 553         .mem_speed = 1600,
 554         .density = 2,
 555         .width = 16,
 556         .banks = 8,
 557         .rowaddr = 14,
 558         .coladdr = 10,
 559         .pagesz = 2,
 560         .trcd = 1375,
 561         .trcmin = 4875,
 562         .trasmin = 3500,
 563 };
 564
 565 static void ccgr_init(void)
 566 {
 567         struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 568
 569         writel(0x00C03F3F, &ccm->CCGR0);
 570         writel(0x0030FC03, &ccm->CCGR1);
 571         writel(0x0FFFC000, &ccm->CCGR2);
 572         writel(0x3FF00000, &ccm->CCGR3);
 573         writel(0x00FFF300, &ccm->CCGR4);
 574         writel(0x0F0000C3, &ccm->CCGR5);
 575         writel(0x000003FF, &ccm->CCGR6);
 576 }
 577
 578 /*
 579  * This section requires the differentiation between iMX6 Sabre boards, but
 580  * for now, it will configure only for the mx6q variant.
 581  */
 582 static void spl_dram_init(void)
 583 {
 584         struct mx6_ddr_sysinfo sysinfo = {
 585                 /* width of data bus:0=16,1=32,2=64 */
 586                 .dsize = 2,
 587                 /* config for full 4GB range so that get_mem_size() works */
 588                 .cs_density = 32, /* 32Gb per CS */
 589                 /* single chip select */
 590                 .ncs = 1,
 591                 .cs1_mirror = 0,
 592                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 593                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 594                 .walat = 1,     /* Write additional latency */
 595                 .ralat = 5,     /* Read additional latency */
 596                 .mif3_mode = 3, /* Command prediction working mode */
 597                 .bi_on = 1,     /* Bank interleaving enabled */
 598                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 599                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 600                 .ddr_type = DDR_TYPE_DDR3,
 601                 .refsel = 1,    /* Refresh cycles at 32KHz */
 602                 .refr = 7,      /* 8 refresh commands per refresh cycle */
 603         };
 604
 605         mx6dq_dram_iocfg(64, &mx6_ddr_ioregs, &mx6_grp_ioregs);
 606         mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr);
 607 }
 608
 609 void board_init_f(ulong dummy)
 610 {
 611         /* setup AIPS and disable watchdog */
 612         arch_cpu_init();
 613
 614         ccgr_init();
 615         gpr_init();
 616
 617         /* iomux and setup of i2c */
 618         board_early_init_f();
 619
 620         /* setup GP timer */
 621         timer_init();
 622
 623         /* UART clocks enabled and gd valid - init serial console */
 624         preloader_console_init();
 625
 626         /* DDR initialization */
 627         spl_dram_init();
 628
 629         /* Clear the BSS. */
 630         memset(__bss_start, 0, __bss_end - __bss_start);
 631
 632         /* load/boot image from boot device */
 633         board_init_r(NULL, 0);
 634 }
 635
 636 #endif