1 // SPDX-License-Identifier: GPL-2.0+
3 * DHCOM DH-iMX6 PDK board support
5 * Copyright (C) 2017 Marek Vasut <marex@denx.de>
14 #include <dm/device-internal.h>
15 #include <asm/arch/clock.h>
16 #include <asm/arch/crm_regs.h>
17 #include <asm/arch/imx-regs.h>
18 #include <asm/arch/iomux.h>
19 #include <asm/arch/mx6-pins.h>
20 #include <asm/arch/sys_proto.h>
23 #include <asm/mach-imx/boot_mode.h>
24 #include <asm/mach-imx/iomux-v3.h>
25 #include <asm/mach-imx/sata.h>
27 #include <dwc_ahsata.h>
30 #include <fsl_esdhc_imx.h>
32 #include <i2c_eeprom.h>
35 #include <linux/delay.h>
36 #include <usb/ehci-ci.h>
38 DECLARE_GLOBAL_DATA_PTR;
42 gd->ram_size = imx_ddr_size();
47 * Do not overwrite the console
48 * Use always serial for U-Boot console
50 int overwrite_console(void)
55 static int setup_fec_clock(void)
57 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
59 /* set gpr1[21] to select anatop clock */
60 clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
62 return enable_fec_anatop_clock(0, ENET_50MHZ);
65 #ifdef CONFIG_USB_EHCI_MX6
66 static void setup_usb(void)
69 * Set daisy chain for otg_pin_id on MX6Q.
70 * For MX6DL, this bit is reserved.
72 imx_iomux_set_gpr_register(1, 13, 1, 0);
75 int board_usb_phy_mode(int port)
80 return USB_INIT_DEVICE;
84 static int setup_dhcom_mac_from_fuse(void)
88 unsigned char enetaddr[6];
91 ret = eth_env_get_enetaddr("ethaddr", enetaddr);
92 if (ret) /* ethaddr is already set */
95 imx_get_mac_from_fuse(0, enetaddr);
97 if (is_valid_ethaddr(enetaddr)) {
98 eth_env_set_enetaddr("ethaddr", enetaddr);
102 eeprom = ofnode_path("/soc/aips-bus@2100000/i2c@21a8000/eeprom@50");
103 if (!ofnode_valid(eeprom)) {
104 printf("Invalid hardware path to EEPROM!\n");
108 ret = uclass_get_device_by_ofnode(UCLASS_I2C_EEPROM, eeprom, &dev);
110 printf("Cannot find EEPROM!\n");
114 ret = i2c_eeprom_read(dev, 0xfa, enetaddr, 0x6);
116 printf("Error reading configuration EEPROM!\n");
120 if (is_valid_ethaddr(enetaddr))
121 eth_env_set_enetaddr("ethaddr", enetaddr);
126 int board_early_init_f(void)
128 #ifdef CONFIG_USB_EHCI_MX6
137 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
139 /* address of boot parameters */
140 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
142 /* Enable eim_slow clocks */
143 setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
145 setup_dhcom_mac_from_fuse();
152 #ifdef CONFIG_CMD_BMODE
153 static const struct boot_mode board_boot_modes[] = {
154 /* 4 bit bus width */
155 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
156 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
157 /* 8 bit bus width */
158 {"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
163 #define HW_CODE_BIT_0 IMX_GPIO_NR(2, 19)
164 #define HW_CODE_BIT_1 IMX_GPIO_NR(6, 6)
165 #define HW_CODE_BIT_2 IMX_GPIO_NR(2, 16)
167 static int board_get_hwcode(void)
171 gpio_request(HW_CODE_BIT_0, "HW-code-bit-0");
172 gpio_request(HW_CODE_BIT_1, "HW-code-bit-1");
173 gpio_request(HW_CODE_BIT_2, "HW-code-bit-2");
175 gpio_direction_input(HW_CODE_BIT_0);
176 gpio_direction_input(HW_CODE_BIT_1);
177 gpio_direction_input(HW_CODE_BIT_2);
179 /* HW 100 + HW 200 = 00b; HW 300 = 01b */
180 hw_code = ((gpio_get_value(HW_CODE_BIT_2) << 2) |
181 (gpio_get_value(HW_CODE_BIT_1) << 1) |
182 gpio_get_value(HW_CODE_BIT_0)) + 2;
187 int board_late_init(void)
192 hw_code = board_get_hwcode();
194 switch (get_cpu_type()) {
195 case MXC_CPU_MX6SOLO:
196 snprintf(buf, sizeof(buf), "imx6s-dhcom%1d", hw_code);
199 snprintf(buf, sizeof(buf), "imx6dl-dhcom%1d", hw_code);
202 snprintf(buf, sizeof(buf), "imx6d-dhcom%1d", hw_code);
205 snprintf(buf, sizeof(buf), "imx6q-dhcom%1d", hw_code);
208 snprintf(buf, sizeof(buf), "UNKNOWN%1d", hw_code);
212 env_set("dhcom", buf);
214 #ifdef CONFIG_CMD_BMODE
215 add_board_boot_modes(board_boot_modes);
222 puts("Board: DHCOM i.MX6\n");
226 #ifdef CONFIG_MULTI_DTB_FIT
227 int board_fit_config_name_match(const char *name)
230 if (!strcmp(name, "imx6q-dhcom-pdk2"))
232 } else if (is_mx6sdl()) {
233 if (!strcmp(name, "imx6dl-dhcom-pdk2"))