board/compulab/cm_t335/cm_t335.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Compulab CM-T335 board
   4  *
   5  * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/
   6  *
   7  * Author: Ilya Ledvich <ilya@compulab.co.il>
   8  */
   9
  10 #include <common.h>
  11 #include <env.h>
  12 #include <errno.h>
  13 #include <miiphy.h>
  14 #include <net.h>
  15 #include <status_led.h>
  16 #include <cpsw.h>
  17 #include <linux/delay.h>
  18
  19 #include <asm/arch/sys_proto.h>
  20 #include <asm/arch/hardware_am33xx.h>
  21 #include <asm/io.h>
  22 #include <asm/gpio.h>
  23
  24 #include "../common/eeprom.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 /*
  29  * Basic board specific setup.  Pinmux has been handled already.
  30  */
  31 int board_init(void)
  32 {
  33         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  34
  35         gpmc_init();
  36
  37 #if defined(CONFIG_LED_STATUS) && defined(CONFIG_LED_STATUS_BOOT_ENABLE)
  38         status_led_set(CONFIG_LED_STATUS_BOOT, CONFIG_LED_STATUS_OFF);
  39 #endif
  40         return 0;
  41 }
  42
  43 #if defined (CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)
  44 static void cpsw_control(int enabled)
  45 {
  46         /* VTP can be added here */
  47         return;
  48 }
  49
  50 static struct cpsw_slave_data cpsw_slave = {
  51         .slave_reg_ofs  = 0x208,
  52         .sliver_reg_ofs = 0xd80,
  53         .phy_addr       = 0,
  54         .phy_if         = PHY_INTERFACE_MODE_RGMII,
  55 };
  56
  57 static struct cpsw_platform_data cpsw_data = {
  58         .mdio_base              = CPSW_MDIO_BASE,
  59         .cpsw_base              = CPSW_BASE,
  60         .mdio_div               = 0xff,
  61         .channels               = 8,
  62         .cpdma_reg_ofs          = 0x800,
  63         .slaves                 = 1,
  64         .slave_data             = &cpsw_slave,
  65         .ale_reg_ofs            = 0xd00,
  66         .ale_entries            = 1024,
  67         .host_port_reg_ofs      = 0x108,
  68         .hw_stats_reg_ofs       = 0x900,
  69         .bd_ram_ofs             = 0x2000,
  70         .mac_control            = (1 << 5),
  71         .control                = cpsw_control,
  72         .host_port_num          = 0,
  73         .version                = CPSW_CTRL_VERSION_2,
  74 };
  75
  76 /* PHY reset GPIO */
  77 #define GPIO_PHY_RST            GPIO_PIN(3, 7)
  78
  79 static void board_phy_init(void)
  80 {
  81         gpio_request(GPIO_PHY_RST, "phy_rst");
  82         gpio_direction_output(GPIO_PHY_RST, 0);
  83         mdelay(2);
  84         gpio_set_value(GPIO_PHY_RST, 1);
  85         mdelay(2);
  86 }
  87
  88 static void get_efuse_mac_addr(uchar *enetaddr)
  89 {
  90         uint32_t mac_hi, mac_lo;
  91         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  92
  93         mac_lo = readl(&cdev->macid0l);
  94         mac_hi = readl(&cdev->macid0h);
  95         enetaddr[0] = mac_hi & 0xFF;
  96         enetaddr[1] = (mac_hi & 0xFF00) >> 8;
  97         enetaddr[2] = (mac_hi & 0xFF0000) >> 16;
  98         enetaddr[3] = (mac_hi & 0xFF000000) >> 24;
  99         enetaddr[4] = mac_lo & 0xFF;
 100         enetaddr[5] = (mac_lo & 0xFF00) >> 8;
 101 }
 102
 103 /*
 104  * Routine: handle_mac_address
 105  * Description: prepare MAC address for on-board Ethernet.
 106  */
 107 static int handle_mac_address(void)
 108 {
 109         uchar enetaddr[6];
 110         int rv;
 111
 112         rv = eth_env_get_enetaddr("ethaddr", enetaddr);
 113         if (rv)
 114                 return 0;
 115
 116         rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS);
 117         if (rv)
 118                 get_efuse_mac_addr(enetaddr);
 119
 120         if (!is_valid_ethaddr(enetaddr))
 121                 return -1;
 122
 123         return eth_env_set_enetaddr("ethaddr", enetaddr);
 124 }
 125
 126 #define AR8051_PHY_DEBUG_ADDR_REG       0x1d
 127 #define AR8051_PHY_DEBUG_DATA_REG       0x1e
 128 #define AR8051_DEBUG_RGMII_CLK_DLY_REG  0x5
 129 #define AR8051_RGMII_TX_CLK_DLY         0x100
 130
 131 int board_eth_init(bd_t *bis)
 132 {
 133         int rv, n = 0;
 134         const char *devname;
 135         struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
 136
 137         rv = handle_mac_address();
 138         if (rv)
 139                 printf("No MAC address found!\n");
 140
 141         writel(RGMII_MODE_ENABLE | RGMII_INT_DELAY, &cdev->miisel);
 142
 143         board_phy_init();
 144
 145         rv = cpsw_register(&cpsw_data);
 146         if (rv < 0)
 147                 printf("Error %d registering CPSW switch\n", rv);
 148         else
 149                 n += rv;
 150
 151         /*
 152          * CPSW RGMII Internal Delay Mode is not supported in all PVT
 153          * operating points.  So we must set the TX clock delay feature
 154          * in the AR8051 PHY.  Since we only support a single ethernet
 155          * device, we only do this for the first instance.
 156          */
 157         devname = miiphy_get_current_dev();
 158
 159         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
 160                      AR8051_DEBUG_RGMII_CLK_DLY_REG);
 161         miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
 162                      AR8051_RGMII_TX_CLK_DLY);
 163         return n;
 164 }
 165 #endif /* CONFIG_DRIVER_TI_CPSW && !CONFIG_SPL_BUILD */