board/compulab/cm_fx6/cm_fx6.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Board functions for Compulab CM-FX6 board
   4  *
   5  * Copyright (C) 2014, Compulab Ltd - http://compulab.co.il/
   6  *
   7  * Author: Nikita Kiryanov <nikita@compulab.co.il>
   8  */
   9
  10 #include <common.h>
  11 #include <ahci.h>
  12 #include <dm.h>
  13 #include <dwc_ahsata.h>
  14 #include <env.h>
  15 #include <fsl_esdhc_imx.h>
  16 #include <init.h>
  17 #include <miiphy.h>
  18 #include <mtd_node.h>
  19 #include <net.h>
  20 #include <netdev.h>
  21 #include <errno.h>
  22 #include <usb.h>
  23 #include <fdt_support.h>
  24 #include <sata.h>
  25 #include <splash.h>
  26 #include <asm/arch/crm_regs.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/iomux.h>
  29 #include <asm/arch/mxc_hdmi.h>
  30 #include <asm/mach-imx/mxc_i2c.h>
  31 #include <asm/mach-imx/sata.h>
  32 #include <asm/mach-imx/video.h>
  33 #include <asm/io.h>
  34 #include <asm/gpio.h>
  35 #include <dm/platform_data/serial_mxc.h>
  36 #include <dm/device-internal.h>
  37 #include <jffs2/load_kernel.h>
  38 #include <linux/delay.h>
  39 #include "common.h"
  40 #include "../common/eeprom.h"
  41 #include "../common/common.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 #ifdef CONFIG_SPLASH_SCREEN
  46 static struct splash_location cm_fx6_splash_locations[] = {
  47         {
  48                 .name = "sf",
  49                 .storage = SPLASH_STORAGE_SF,
  50                 .flags = SPLASH_STORAGE_RAW,
  51                 .offset = 0x100000,
  52         },
  53         {
  54                 .name = "mmc_fs",
  55                 .storage = SPLASH_STORAGE_MMC,
  56                 .flags = SPLASH_STORAGE_FS,
  57                 .devpart = "2:1",
  58         },
  59         {
  60                 .name = "usb_fs",
  61                 .storage = SPLASH_STORAGE_USB,
  62                 .flags = SPLASH_STORAGE_FS,
  63                 .devpart = "0:1",
  64         },
  65         {
  66                 .name = "sata_fs",
  67                 .storage = SPLASH_STORAGE_SATA,
  68                 .flags = SPLASH_STORAGE_FS,
  69                 .devpart = "0:1",
  70         },
  71 };
  72
  73 int splash_screen_prepare(void)
  74 {
  75         return splash_source_load(cm_fx6_splash_locations,
  76                                   ARRAY_SIZE(cm_fx6_splash_locations));
  77 }
  78 #endif
  79
  80 #ifdef CONFIG_IMX_HDMI
  81 static void cm_fx6_enable_hdmi(struct display_info_t const *dev)
  82 {
  83         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  84         imx_setup_hdmi();
  85         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
  86         imx_enable_hdmi_phy();
  87 }
  88
  89 static struct display_info_t preset_hdmi_1024X768 = {
  90         .bus    = -1,
  91         .addr   = 0,
  92         .pixfmt = IPU_PIX_FMT_RGB24,
  93         .enable = cm_fx6_enable_hdmi,
  94         .mode   = {
  95                 .name           = "HDMI",
  96                 .refresh        = 60,
  97                 .xres           = 1024,
  98                 .yres           = 768,
  99                 .pixclock       = 40385,
 100                 .left_margin    = 220,
 101                 .right_margin   = 40,
 102                 .upper_margin   = 21,
 103                 .lower_margin   = 7,
 104                 .hsync_len      = 60,
 105                 .vsync_len      = 10,
 106                 .sync           = FB_SYNC_EXT,
 107                 .vmode          = FB_VMODE_NONINTERLACED,
 108         }
 109 };
 110
 111 static void cm_fx6_setup_display(void)
 112 {
 113         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 114
 115         enable_ipu_clock();
 116         clrbits_le32(&iomuxc_regs->gpr[3], MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK);
 117 }
 118
 119 int board_video_skip(void)
 120 {
 121         int ret;
 122         struct display_info_t *preset;
 123         char const *panel = env_get("displaytype");
 124
 125         if (!panel) /* Also accept panel for backward compatibility */
 126                 panel = env_get("panel");
 127
 128         if (!panel)
 129                 return -ENOENT;
 130
 131         if (!strcmp(panel, "HDMI"))
 132                 preset = &preset_hdmi_1024X768;
 133         else
 134                 return -EINVAL;
 135
 136         ret = ipuv3_fb_init(&preset->mode, 0, preset->pixfmt);
 137         if (ret) {
 138                 printf("Can't init display %s: %d\n", preset->mode.name, ret);
 139                 return ret;
 140         }
 141
 142         preset->enable(preset);
 143         printf("Display: %s (%ux%u)\n", preset->mode.name, preset->mode.xres,
 144                preset->mode.yres);
 145
 146         return 0;
 147 }
 148 #else
 149 static inline void cm_fx6_setup_display(void) {}
 150 #endif /* CONFIG_VIDEO_IPUV3 */
 151
 152 int ipu_displays_init(void)
 153 {
 154         return board_video_skip();
 155 }
 156
 157 #ifdef CONFIG_DWC_AHSATA
 158 static int cm_fx6_issd_gpios[] = {
 159         /* The order of the GPIOs in the array is important! */
 160         CM_FX6_SATA_LDO_EN,
 161         CM_FX6_SATA_PHY_SLP,
 162         CM_FX6_SATA_NRSTDLY,
 163         CM_FX6_SATA_PWREN,
 164         CM_FX6_SATA_NSTANDBY1,
 165         CM_FX6_SATA_NSTANDBY2,
 166 };
 167
 168 static void cm_fx6_sata_power(int on)
 169 {
 170         int i;
 171
 172         if (!on) { /* tell the iSSD that the power will be removed */
 173                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 1);
 174                 mdelay(10);
 175         }
 176
 177         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 178                 gpio_direction_output(cm_fx6_issd_gpios[i], on);
 179                 udelay(100);
 180         }
 181
 182         if (!on) /* for compatibility lower the power loss interrupt */
 183                 gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 184 }
 185
 186 static iomux_v3_cfg_t const sata_pads[] = {
 187         /* SATA PWR */
 188         IOMUX_PADS(PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 189         IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 190         IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 191         IOMUX_PADS(PAD_EIM_A25__GPIO5_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 192         /* SATA CTRL */
 193         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 194         IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 195         IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 196         IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 197         IOMUX_PADS(PAD_EIM_BCLK__GPIO6_IO31   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 198 };
 199
 200 static int cm_fx6_setup_issd(void)
 201 {
 202         int ret, i;
 203
 204         SETUP_IOMUX_PADS(sata_pads);
 205
 206         for (i = 0; i < ARRAY_SIZE(cm_fx6_issd_gpios); i++) {
 207                 ret = gpio_request(cm_fx6_issd_gpios[i], "sata");
 208                 if (ret)
 209                         return ret;
 210         }
 211
 212         ret = gpio_request(CM_FX6_SATA_PWLOSS_INT, "sata_pwloss_int");
 213         if (ret)
 214                 return ret;
 215
 216         return 0;
 217 }
 218
 219 #define CM_FX6_SATA_INIT_RETRIES        10
 220
 221 #else
 222 static int cm_fx6_setup_issd(void) { return 0; }
 223 #endif
 224
 225 #ifdef CONFIG_SYS_I2C_MXC
 226 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 227                         PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
 228                         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 229
 230 I2C_PADS(i2c0_pads,
 231          PAD_EIM_D21__I2C1_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 232          PAD_EIM_D21__GPIO3_IO21 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 233          IMX_GPIO_NR(3, 21),
 234          PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 235          PAD_EIM_D28__GPIO3_IO28 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 236          IMX_GPIO_NR(3, 28));
 237
 238 I2C_PADS(i2c1_pads,
 239          PAD_KEY_COL3__I2C2_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 240          PAD_KEY_COL3__GPIO4_IO12 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 241          IMX_GPIO_NR(4, 12),
 242          PAD_KEY_ROW3__I2C2_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 243          PAD_KEY_ROW3__GPIO4_IO13 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 244          IMX_GPIO_NR(4, 13));
 245
 246 I2C_PADS(i2c2_pads,
 247          PAD_GPIO_3__I2C3_SCL | MUX_PAD_CTRL(I2C_PAD_CTRL),
 248          PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 249          IMX_GPIO_NR(1, 3),
 250          PAD_GPIO_6__I2C3_SDA | MUX_PAD_CTRL(I2C_PAD_CTRL),
 251          PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(I2C_PAD_CTRL),
 252          IMX_GPIO_NR(1, 6));
 253
 254
 255 static int cm_fx6_setup_one_i2c(int busnum, struct i2c_pads_info *pads)
 256 {
 257         int ret;
 258
 259         ret = setup_i2c(busnum, CONFIG_SYS_I2C_SPEED, 0x7f, pads);
 260         if (ret)
 261                 printf("Warning: I2C%d setup failed: %d\n", busnum, ret);
 262
 263         return ret;
 264 }
 265
 266 static int cm_fx6_setup_i2c(void)
 267 {
 268         int ret = 0, err;
 269
 270         /* i2c<x>_pads are wierd macro variables; we can't use an array */
 271         err = cm_fx6_setup_one_i2c(0, I2C_PADS_INFO(i2c0_pads));
 272         if (err)
 273                 ret = err;
 274         err = cm_fx6_setup_one_i2c(1, I2C_PADS_INFO(i2c1_pads));
 275         if (err)
 276                 ret = err;
 277         err = cm_fx6_setup_one_i2c(2, I2C_PADS_INFO(i2c2_pads));
 278         if (err)
 279                 ret = err;
 280
 281         return ret;
 282 }
 283 #else
 284 static int cm_fx6_setup_i2c(void) { return 0; }
 285 #endif
 286
 287 #ifdef CONFIG_USB_EHCI_MX6
 288 #define WEAK_PULLDOWN   (PAD_CTL_PUS_100K_DOWN |                \
 289                         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
 290                         PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
 291 #define MX6_USBNC_BASEADDR      0x2184800
 292 #define USBNC_USB_H1_PWR_POL    (1 << 9)
 293
 294 static int cm_fx6_setup_usb_host(void)
 295 {
 296         int err;
 297
 298         err = gpio_request(CM_FX6_USB_HUB_RST, "usb hub rst");
 299         if (err)
 300                 return err;
 301
 302         SETUP_IOMUX_PAD(PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL));
 303         SETUP_IOMUX_PAD(PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL));
 304
 305         return 0;
 306 }
 307
 308 static int cm_fx6_setup_usb_otg(void)
 309 {
 310         int err;
 311         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 312
 313         err = gpio_request(SB_FX6_USB_OTG_PWR, "usb-pwr");
 314         if (err) {
 315                 printf("USB OTG pwr gpio request failed: %d\n", err);
 316                 return err;
 317         }
 318
 319         SETUP_IOMUX_PAD(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL));
 320         SETUP_IOMUX_PAD(PAD_ENET_RX_ER__USB_OTG_ID |
 321                                                 MUX_PAD_CTRL(WEAK_PULLDOWN));
 322         clrbits_le32(&iomux->gpr[1], IOMUXC_GPR1_OTG_ID_MASK);
 323         /* disable ext. charger detect, or it'll affect signal quality at dp. */
 324         return gpio_direction_output(SB_FX6_USB_OTG_PWR, 0);
 325 }
 326
 327 int board_usb_phy_mode(int port)
 328 {
 329         return USB_INIT_HOST;
 330 }
 331
 332 int board_ehci_hcd_init(int port)
 333 {
 334         int ret;
 335         u32 *usbnc_usb_uh1_ctrl = (u32 *)(MX6_USBNC_BASEADDR + 4);
 336
 337         /* Only 1 host controller in use. port 0 is OTG & needs no attention */
 338         if (port != 1)
 339                 return 0;
 340
 341         /* Set PWR polarity to match power switch's enable polarity */
 342         setbits_le32(usbnc_usb_uh1_ctrl, USBNC_USB_H1_PWR_POL);
 343         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 0);
 344         if (ret)
 345                 return ret;
 346
 347         udelay(10);
 348         ret = gpio_direction_output(CM_FX6_USB_HUB_RST, 1);
 349         if (ret)
 350                 return ret;
 351
 352         mdelay(1);
 353
 354         return 0;
 355 }
 356
 357 int board_ehci_power(int port, int on)
 358 {
 359         if (port == 0)
 360                 return gpio_direction_output(SB_FX6_USB_OTG_PWR, on);
 361
 362         return 0;
 363 }
 364 #else
 365 static int cm_fx6_setup_usb_otg(void) { return 0; }
 366 static int cm_fx6_setup_usb_host(void) { return 0; }
 367 #endif
 368
 369 #ifdef CONFIG_FEC_MXC
 370 #define ENET_PAD_CTRL           (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
 371                                  PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 372
 373 static int mx6_rgmii_rework(struct phy_device *phydev)
 374 {
 375         unsigned short val;
 376
 377         /* Ar8031 phy SmartEEE feature cause link status generates glitch,
 378          * which cause ethernet link down/up issue, so disable SmartEEE
 379          */
 380         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3);
 381         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d);
 382         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003);
 383         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 384         val &= ~(0x1 << 8);
 385         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 386
 387         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 388         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 389         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 390         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 391
 392         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 393         val &= 0xffe3;
 394         val |= 0x18;
 395         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 396
 397         /* introduce tx clock delay */
 398         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 399         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 400         val |= 0x0100;
 401         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 402
 403         return 0;
 404 }
 405
 406 int board_phy_config(struct phy_device *phydev)
 407 {
 408         mx6_rgmii_rework(phydev);
 409
 410         if (phydev->drv->config)
 411                 return phydev->drv->config(phydev);
 412
 413         return 0;
 414 }
 415
 416 static iomux_v3_cfg_t const enet_pads[] = {
 417         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 418         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 419         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 420         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 421         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 422         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 423         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 424         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 425         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 426         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 427         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 428         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 429         IOMUX_PADS(PAD_GPIO_0__CCM_CLKO1    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 430         IOMUX_PADS(PAD_GPIO_3__CCM_CLKO2    | MUX_PAD_CTRL(NO_PAD_CTRL)),
 431         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(0x84)),
 432         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK  |
 433                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 434         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 435                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 436         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 437                                                 MUX_PAD_CTRL(ENET_PAD_CTRL)),
 438 };
 439
 440 static int handle_mac_address(char *env_var, uint eeprom_bus)
 441 {
 442         unsigned char enetaddr[6];
 443         int rc;
 444
 445         rc = eth_env_get_enetaddr(env_var, enetaddr);
 446         if (rc)
 447                 return 0;
 448
 449         rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus);
 450         if (rc)
 451                 return rc;
 452
 453         if (!is_valid_ethaddr(enetaddr))
 454                 return -1;
 455
 456         return eth_env_set_enetaddr(env_var, enetaddr);
 457 }
 458
 459 #define SB_FX6_I2C_EEPROM_BUS   0
 460 #define NO_MAC_ADDR             "No MAC address found for %s\n"
 461 int board_eth_init(bd_t *bis)
 462 {
 463         int err;
 464
 465         if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS))
 466                 printf(NO_MAC_ADDR, "primary NIC");
 467
 468         if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS))
 469                 printf(NO_MAC_ADDR, "secondary NIC");
 470
 471         SETUP_IOMUX_PADS(enet_pads);
 472         /* phy reset */
 473         err = gpio_request(CM_FX6_ENET_NRST, "enet_nrst");
 474         if (err)
 475                 printf("Etnernet NRST gpio request failed: %d\n", err);
 476         gpio_direction_output(CM_FX6_ENET_NRST, 0);
 477         udelay(500);
 478         gpio_set_value(CM_FX6_ENET_NRST, 1);
 479         enable_enet_clk(1);
 480         return cpu_eth_init(bis);
 481 }
 482 #endif
 483
 484 #ifdef CONFIG_NAND_MXS
 485 static iomux_v3_cfg_t const nand_pads[] = {
 486         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 487         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 488         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 489         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 490         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 491         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 492         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 493         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 494         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 495         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 496         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 497         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 498         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 499         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 500 };
 501
 502 static void cm_fx6_setup_gpmi_nand(void)
 503 {
 504         SETUP_IOMUX_PADS(nand_pads);
 505         /* Enable clock roots */
 506         enable_usdhc_clk(1, 3);
 507         enable_usdhc_clk(1, 4);
 508
 509         setup_gpmi_io_clk(MXC_CCM_CS2CDR_ENFC_CLK_PODF(0xf) |
 510                           MXC_CCM_CS2CDR_ENFC_CLK_PRED(1)   |
 511                           MXC_CCM_CS2CDR_ENFC_CLK_SEL(0));
 512 }
 513 #else
 514 static void cm_fx6_setup_gpmi_nand(void) {}
 515 #endif
 516
 517 #ifdef CONFIG_MXC_SPI
 518 int cm_fx6_setup_ecspi(void)
 519 {
 520         cm_fx6_set_ecspi_iomux();
 521         return gpio_request(CM_FX6_ECSPI_BUS0_CS0, "ecspi_bus0_cs0");
 522 }
 523 #else
 524 int cm_fx6_setup_ecspi(void) { return 0; }
 525 #endif
 526
 527 #ifdef CONFIG_OF_BOARD_SETUP
 528 #define USDHC3_PATH     "/soc/aips-bus@02100000/usdhc@02198000/"
 529
 530 static const struct node_info nodes[] = {
 531         /*
 532          * Both entries target the same flash chip. The st,m25p compatible
 533          * is used in the vendor device trees, while upstream uses (the
 534          * documented) jedec,spi-nor compatible.
 535          */
 536         { "st,m25p",    MTD_DEV_TYPE_NOR,       },
 537         { "jedec,spi-nor",      MTD_DEV_TYPE_NOR,       },
 538 };
 539
 540 int ft_board_setup(void *blob, bd_t *bd)
 541 {
 542         u32 baseboard_rev;
 543         int nodeoffset;
 544         uint8_t enetaddr[6];
 545         char baseboard_name[16];
 546         int err;
 547
 548         fdt_shrink_to_minimum(blob, 0); /* Make room for new properties */
 549
 550         /* MAC addr */
 551         if (eth_env_get_enetaddr("ethaddr", enetaddr)) {
 552                 fdt_find_and_setprop(blob,
 553                                      "/soc/aips-bus@02100000/ethernet@02188000",
 554                                      "local-mac-address", enetaddr, 6, 1);
 555         }
 556
 557         if (eth_env_get_enetaddr("eth1addr", enetaddr)) {
 558                 fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address",
 559                                      enetaddr, 6, 1);
 560         }
 561
 562         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
 563
 564         baseboard_rev = cl_eeprom_get_board_rev(0);
 565         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 566         if (err || baseboard_rev == 0)
 567                 return 0; /* Assume not an early revision SB-FX6m baseboard */
 568
 569         if (!strncmp("SB-FX6m", baseboard_name, 7) && baseboard_rev <= 120) {
 570                 nodeoffset = fdt_path_offset(blob, USDHC3_PATH);
 571                 fdt_delprop(blob, nodeoffset, "cd-gpios");
 572                 fdt_find_and_setprop(blob, USDHC3_PATH, "broken-cd",
 573                                      NULL, 0, 1);
 574                 fdt_find_and_setprop(blob, USDHC3_PATH, "keep-power-in-suspend",
 575                                      NULL, 0, 1);
 576         }
 577
 578         return 0;
 579 }
 580 #endif
 581
 582 int board_init(void)
 583 {
 584         int ret;
 585
 586         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 587         cm_fx6_setup_gpmi_nand();
 588
 589         ret = cm_fx6_setup_ecspi();
 590         if (ret)
 591                 printf("Warning: ECSPI setup failed: %d\n", ret);
 592
 593         ret = cm_fx6_setup_usb_otg();
 594         if (ret)
 595                 printf("Warning: USB OTG setup failed: %d\n", ret);
 596
 597         ret = cm_fx6_setup_usb_host();
 598         if (ret)
 599                 printf("Warning: USB host setup failed: %d\n", ret);
 600
 601         /*
 602          * cm-fx6 may have iSSD not assembled and in this case it has
 603          * bypasses for a (m)SATA socket on the baseboard. The socketed
 604          * device is not controlled by those GPIOs. So just print a warning
 605          * if the setup fails.
 606          */
 607         ret = cm_fx6_setup_issd();
 608         if (ret)
 609                 printf("Warning: iSSD setup failed: %d\n", ret);
 610
 611         /* Warn on failure but do not abort boot */
 612         ret = cm_fx6_setup_i2c();
 613         if (ret)
 614                 printf("Warning: I2C setup failed: %d\n", ret);
 615
 616         cm_fx6_setup_display();
 617
 618         /* This should be done in the MMC driver when MX6 has a clock driver */
 619 #ifdef CONFIG_FSL_ESDHC_IMX
 620         if (IS_ENABLED(CONFIG_BLK)) {
 621                 int i;
 622
 623                 cm_fx6_set_usdhc_iomux();
 624                 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
 625                         enable_usdhc_clk(1, i);
 626         }
 627 #endif
 628
 629         return 0;
 630 }
 631
 632 int board_late_init(void)
 633 {
 634 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 635         char baseboard_name[16];
 636         int err;
 637
 638         if (is_mx6dq())
 639                 env_set("board_rev", "MX6Q");
 640         else if (is_mx6dl())
 641                 env_set("board_rev", "MX6DL");
 642
 643         err = cl_eeprom_get_product_name((uchar *)baseboard_name, 0);
 644         if (err)
 645                 return 0;
 646
 647         if (!strncmp("SB-FX6m", baseboard_name, 7))
 648                 env_set("board_name", "Utilite");
 649 #endif
 650         return 0;
 651 }
 652
 653 int checkboard(void)
 654 {
 655         puts("Board: CM-FX6\n");
 656         return 0;
 657 }
 658
 659 int misc_init_r(void)
 660 {
 661         cl_print_pcb_info();
 662
 663         return 0;
 664 }
 665
 666 int dram_init_banksize(void)
 667 {
 668         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 669         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 670
 671         switch (gd->ram_size) {
 672         case 0x10000000: /* DDR_16BIT_256MB */
 673                 gd->bd->bi_dram[0].size = 0x10000000;
 674                 gd->bd->bi_dram[1].size = 0;
 675                 break;
 676         case 0x20000000: /* DDR_32BIT_512MB */
 677                 gd->bd->bi_dram[0].size = 0x20000000;
 678                 gd->bd->bi_dram[1].size = 0;
 679                 break;
 680         case 0x40000000:
 681                 if (is_cpu_type(MXC_CPU_MX6SOLO)) { /* DDR_32BIT_1GB */
 682                         gd->bd->bi_dram[0].size = 0x20000000;
 683                         gd->bd->bi_dram[1].size = 0x20000000;
 684                 } else { /* DDR_64BIT_1GB */
 685                         gd->bd->bi_dram[0].size = 0x40000000;
 686                         gd->bd->bi_dram[1].size = 0;
 687                 }
 688                 break;
 689         case 0x80000000: /* DDR_64BIT_2GB */
 690                 gd->bd->bi_dram[0].size = 0x40000000;
 691                 gd->bd->bi_dram[1].size = 0x40000000;
 692                 break;
 693         case 0xEFF00000: /* DDR_64BIT_4GB */
 694                 gd->bd->bi_dram[0].size = 0x70000000;
 695                 gd->bd->bi_dram[1].size = 0x7FF00000;
 696                 break;
 697         }
 698
 699         return 0;
 700 }
 701
 702 int dram_init(void)
 703 {
 704         gd->ram_size = imx_ddr_size();
 705         switch (gd->ram_size) {
 706         case 0x10000000:
 707         case 0x20000000:
 708         case 0x40000000:
 709         case 0x80000000:
 710                 break;
 711         case 0xF0000000:
 712                 gd->ram_size -= 0x100000;
 713                 break;
 714         default:
 715                 printf("ERROR: Unsupported DRAM size 0x%lx\n", gd->ram_size);
 716                 return -1;
 717         }
 718
 719         return 0;
 720 }
 721
 722 u32 get_board_rev(void)
 723 {
 724         return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
 725 }
 726
 727 static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
 728         .reg = (struct mxc_uart *)UART4_BASE,
 729 };
 730
 731 U_BOOT_DEVICE(cm_fx6_serial) = {
 732         .name   = "serial_mxc",
 733         .platdata = &cm_fx6_mxc_serial_plat,
 734 };
 735
 736 #if CONFIG_IS_ENABLED(AHCI)
 737 static int sata_imx_probe(struct udevice *dev)
 738 {
 739         int i, err;
 740
 741         /* Make sure this gpio has logical 0 value */
 742         gpio_direction_output(CM_FX6_SATA_PWLOSS_INT, 0);
 743         udelay(100);
 744         cm_fx6_sata_power(1);
 745
 746         for (i = 0; i < CM_FX6_SATA_INIT_RETRIES; i++) {
 747                 err = setup_sata();
 748                 if (err) {
 749                         printf("SATA setup failed: %d\n", err);
 750                         return err;
 751                 }
 752
 753                 udelay(100);
 754
 755                 err = dwc_ahsata_probe(dev);
 756                 if (!err)
 757                         break;
 758
 759                 /* There is no device on the SATA port */
 760                 if (sata_dm_port_status(0, 0) == 0)
 761                         break;
 762
 763                 /* There's a device, but link not established. Retry */
 764                 device_remove(dev, DM_REMOVE_NORMAL);
 765         }
 766
 767         return 0;
 768 }
 769
 770 static int sata_imx_remove(struct udevice *dev)
 771 {
 772         cm_fx6_sata_power(0);
 773         mdelay(250);
 774
 775         return 0;
 776 }
 777
 778 struct ahci_ops sata_imx_ops = {
 779         .port_status = dwc_ahsata_port_status,
 780         .reset  = dwc_ahsata_bus_reset,
 781         .scan   = dwc_ahsata_scan,
 782 };
 783
 784 static const struct udevice_id sata_imx_ids[] = {
 785         { .compatible = "fsl,imx6q-ahci" },
 786         { }
 787 };
 788
 789 U_BOOT_DRIVER(sata_imx) = {
 790         .name           = "dwc_ahci",
 791         .id             = UCLASS_AHCI,
 792         .of_match       = sata_imx_ids,
 793         .ops            = &sata_imx_ops,
 794         .probe          = sata_imx_probe,
 795         .remove         = sata_imx_remove,  /* reset bus to stop it */
 796 };
 797 #endif /* AHCI */