1 // SPDX-License-Identifier: GPL-2.0+
4 * David Purdy <david.c.purdy@gmail.com>
6 * Based on Kirkwood support:
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
17 #include <asm/arch/cpu.h>
18 #include <asm/arch/soc.h>
19 #include <asm/arch/mpp.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 int board_early_init_f(void)
27 * default gpio configuration
28 * There are maximum 64 gpios controlled through 2 sets of registers
29 * the below configuration configures mainly initial LED status
31 mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
33 POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
35 /* Multi-Purpose Pins Functionality configuration */
36 static const u32 kwmpp_config[] = {
57 MPP29_TSMP9, /* USB Power Enable */
58 MPP48_GPIO, /* LED green */
59 MPP49_GPIO, /* LED orange */
62 kirkwood_mpp_conf(kwmpp_config, NULL);
68 /* Boot parameters address */
69 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
74 #ifdef CONFIG_RESET_PHY_R
75 /* Configure and initialize PHY */
80 char *name = "egiga0";
82 if (miiphy_set_current_dev(name))
85 /* command to read PHY dev address */
86 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
87 printf("Err..(%s) could not read PHY dev address\n", __func__);
92 * Enable RGMII delay on Tx and Rx for CPU port
93 * Ref: sec 4.7.2 of chip datasheet
95 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
96 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
97 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
98 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
99 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
102 miiphy_reset(name, devadr);
104 debug("88E1116 Initialized on %s\n", name);
106 #endif /* CONFIG_RESET_PHY_R */