board/bosch/guardian/board.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * board.c
   4  *
   5  * Board functions for Bosch Guardian
   6  *
   7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
   8  * Copyright (C) 2018 Robert Bosch Power Tools GmbH
   9  */
  10
  11 #include <common.h>
  12 #include <cpsw.h>
  13 #include <dm.h>
  14 #include <env.h>
  15 #include <env_internal.h>
  16 #include <errno.h>
  17 #include <i2c.h>
  18 #include <init.h>
  19 #include <led.h>
  20 #include <miiphy.h>
  21 #include <panel.h>
  22 #include <power/tps65217.h>
  23 #include <power/tps65910.h>
  24 #include <spl.h>
  25 #include <watchdog.h>
  26 #include <asm/arch/clock.h>
  27 #include <asm/arch/cpu.h>
  28 #include <asm/arch/ddr_defs.h>
  29 #include <asm/arch/gpio.h>
  30 #include <asm/arch/hardware.h>
  31 #include <asm/arch/mem.h>
  32 #include <asm/arch/mmc_host_def.h>
  33 #include <asm/arch/omap.h>
  34 #include <asm/arch/sys_proto.h>
  35 #include <asm/emif.h>
  36 #include <asm/gpio.h>
  37 #include <asm/io.h>
  38 #include "board.h"
  39
  40 DECLARE_GLOBAL_DATA_PTR;
  41
  42 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  44
  45 static const struct ddr_data ddr3_data = {
  46         .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  47         .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  48         .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  49         .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  50 };
  51
  52 static const struct cmd_control ddr3_cmd_ctrl_data = {
  53         .cmd0csratio = MT41K128M16JT125K_RATIO,
  54         .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  55
  56         .cmd1csratio = MT41K128M16JT125K_RATIO,
  57         .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  58
  59         .cmd2csratio = MT41K128M16JT125K_RATIO,
  60         .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  61 };
  62
  63 static struct emif_regs ddr3_emif_reg_data = {
  64         .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  65         .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  66         .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  67         .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  68         .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  69         .zq_config = MT41K128M16JT125K_ZQ_CFG,
  70         .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  71 };
  72
  73 #define OSC     (V_OSCK / 1000000)
  74 const struct dpll_params dpll_ddr = {
  75                 400, OSC - 1, 1, -1, -1, -1, -1};
  76
  77 void am33xx_spl_board_init(void)
  78 {
  79         int mpu_vdd;
  80         int usb_cur_lim;
  81
  82         /* Get the frequency */
  83         dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  84
  85         if (i2c_probe(TPS65217_CHIP_PM))
  86                 return;
  87
  88         /*
  89          * Increase USB current limit to 1300mA or 1800mA and set
  90          * the MPU voltage controller as needed.
  91          */
  92         if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  93                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  94                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  95         } else {
  96                 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  97                 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  98         }
  99
 100         if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
 101                                TPS65217_POWER_PATH,
 102                                usb_cur_lim,
 103                                TPS65217_USB_INPUT_CUR_LIMIT_MASK))
 104                 puts("tps65217_reg_write failure\n");
 105
 106         /* Set DCDC3 (CORE) voltage to 1.125V */
 107         if (tps65217_voltage_update(TPS65217_DEFDCDC3,
 108                                     TPS65217_DCDC_VOLT_SEL_1125MV)) {
 109                 puts("tps65217_voltage_update failure\n");
 110                 return;
 111         }
 112
 113         /* Set CORE Frequencies to OPP100 */
 114         do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
 115
 116         /* Set DCDC2 (MPU) voltage */
 117         if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
 118                 puts("tps65217_voltage_update failure\n");
 119                 return;
 120         }
 121
 122         /*
 123          * Set LDO3 to 1.8V and LDO4 to 3.3V
 124          */
 125         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 126                                TPS65217_DEFLS1,
 127                                TPS65217_LDO_VOLTAGE_OUT_1_8,
 128                                TPS65217_LDO_MASK))
 129                 puts("tps65217_reg_write failure\n");
 130
 131         if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
 132                                TPS65217_DEFLS2,
 133                                TPS65217_LDO_VOLTAGE_OUT_3_3,
 134                                TPS65217_LDO_MASK))
 135                 puts("tps65217_reg_write failure\n");
 136
 137         /* Set MPU Frequency to what we detected now that voltages are set */
 138         do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
 139 }
 140
 141 const struct dpll_params *get_dpll_ddr_params(void)
 142 {
 143         enable_i2c0_pin_mux();
 144         i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
 145
 146         return &dpll_ddr;
 147 }
 148
 149 void set_uart_mux_conf(void)
 150 {
 151         enable_uart0_pin_mux();
 152 }
 153
 154 void set_mux_conf_regs(void)
 155 {
 156         enable_board_pin_mux();
 157 }
 158
 159 const struct ctrl_ioregs ioregs = {
 160         .cm0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 161         .cm1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 162         .cm2ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 163         .dt0ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 164         .dt1ioctl               = MT41K128M16JT125K_IOCTRL_VALUE,
 165 };
 166
 167 void sdram_init(void)
 168 {
 169         config_ddr(400, &ioregs,
 170                    &ddr3_data,
 171                    &ddr3_cmd_ctrl_data,
 172                    &ddr3_emif_reg_data, 0);
 173 }
 174 #endif
 175
 176 int board_init(void)
 177 {
 178         save_omap_boot_params();
 179
 180 #if defined(CONFIG_HW_WATCHDOG)
 181         hw_watchdog_init();
 182 #endif
 183
 184         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 185
 186 #ifdef CONFIG_MTD_RAW_NAND
 187         gpmc_init();
 188 #endif
 189         return 0;
 190 }
 191
 192 #ifdef CONFIG_BOARD_LATE_INIT
 193 static void set_bootmode_env(void)
 194 {
 195         char *boot_device_name = NULL;
 196         char *boot_mode_gpio = "gpio@44e07000_14";
 197         int   ret;
 198         int   value;
 199
 200         struct gpio_desc boot_mode_desc;
 201
 202         switch (gd->arch.omap_boot_device) {
 203         case BOOT_DEVICE_NAND:
 204                 boot_device_name = "nand";
 205                 break;
 206         case BOOT_DEVICE_USBETH:
 207                 boot_device_name = "usbeth";
 208                 break;
 209         default:
 210                 break;
 211         }
 212
 213         if (boot_device_name)
 214                 env_set("boot_device", boot_device_name);
 215
 216         ret = dm_gpio_lookup_name(boot_mode_gpio, &boot_mode_desc);
 217         if (ret) {
 218                 printf("%s is not found\n", boot_mode_gpio);
 219                 goto err;
 220         }
 221
 222         ret = dm_gpio_request(&boot_mode_desc, "setup_bootmode_env");
 223         if (ret && ret != -EBUSY) {
 224                 printf("requesting gpio: %s failed\n", boot_mode_gpio);
 225                 goto err;
 226         }
 227
 228         value = dm_gpio_get_value(&boot_mode_desc);
 229         value ? env_set("swi_status", "0") : env_set("swi_status", "1");
 230         return;
 231
 232 err:
 233         env_set("swi_status", "err");
 234 }
 235
 236 int board_late_init(void)
 237 {
 238 #ifdef CONFIG_LED_GPIO
 239         led_default_state();
 240 #endif
 241         set_bootmode_env();
 242         return 0;
 243 }
 244 #endif /* CONFIG_BOARD_LATE_INIT */