board/barco/platinum/spl_titanium.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   4  *
   5  * Based on: gw_ventana_spl.c which is:
   6  * Copyright (C) 2014 Gateworks Corporation
   7  */
   8
   9 #include <common.h>
  10 #include <i2c.h>
  11 #include <init.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-ddr.h>
  15 #include <asm/arch/mx6-pins.h>
  16 #include <asm/arch/sys_proto.h>
  17 #include <asm/mach-imx/boot_mode.h>
  18 #include <asm/mach-imx/iomux-v3.h>
  19 #include <asm/mach-imx/mxc_i2c.h>
  20 #include <spl.h>
  21
  22 #include "platinum.h"
  23
  24 #undef RTT_NOM_120OHM   /* use 120ohm Rtt_nom vs 60ohm (lower power) */
  25
  26 /* Configure MX6Q/DUAL mmdc DDR io registers */
  27 struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
  28         /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
  29         .dram_sdclk_0 = 0x00020030,
  30         .dram_sdclk_1 = 0x00020030,
  31         .dram_cas = 0x00020030,
  32         .dram_ras = 0x00020030,
  33         .dram_reset = 0x00020030,
  34         /* SDCKE[0:1]: 100k pull-up */
  35         .dram_sdcke0 = 0x00003000,
  36         .dram_sdcke1 = 0x00003000,
  37         /* SDBA2: pull-up disabled */
  38         .dram_sdba2 = 0x00000000,
  39         /* SDODT[0:1]: 100k pull-up, 40 ohm */
  40         .dram_sdodt0 = 0x00003030,
  41         .dram_sdodt1 = 0x00003030,
  42         /* SDQS[0:7]: Differential input, 40 ohm */
  43         .dram_sdqs0 = 0x00000030,
  44         .dram_sdqs1 = 0x00000030,
  45         .dram_sdqs2 = 0x00000030,
  46         .dram_sdqs3 = 0x00000030,
  47         .dram_sdqs4 = 0x00000030,
  48         .dram_sdqs5 = 0x00000030,
  49         .dram_sdqs6 = 0x00000030,
  50         .dram_sdqs7 = 0x00000030,
  51         /* DQM[0:7]: Differential input, 40 ohm */
  52         .dram_dqm0 = 0x00020030,
  53         .dram_dqm1 = 0x00020030,
  54         .dram_dqm2 = 0x00020030,
  55         .dram_dqm3 = 0x00020030,
  56         .dram_dqm4 = 0x00020030,
  57         .dram_dqm5 = 0x00020030,
  58         .dram_dqm6 = 0x00020030,
  59         .dram_dqm7 = 0x00020030,
  60 };
  61
  62 /* Configure MX6Q/DUAL mmdc GRP io registers */
  63 struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
  64         /* DDR3 */
  65         .grp_ddr_type = 0x000c0000,
  66         .grp_ddrmode_ctl = 0x00020000,
  67         /* disable DDR pullups */
  68         .grp_ddrpke = 0x00000000,
  69         /* ADDR[00:16], SDBA[0:1]: 40 ohm */
  70         .grp_addds = 0x00000030,
  71         /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
  72         .grp_ctlds = 0x00000030,
  73         /* DATA[00:63]: Differential input, 40 ohm */
  74         .grp_ddrmode = 0x00020000,
  75         .grp_b0ds = 0x00000030,
  76         .grp_b1ds = 0x00000030,
  77         .grp_b2ds = 0x00000030,
  78         .grp_b3ds = 0x00000030,
  79         .grp_b4ds = 0x00000030,
  80         .grp_b5ds = 0x00000030,
  81         .grp_b6ds = 0x00000030,
  82         .grp_b7ds = 0x00000030,
  83 };
  84
  85 /* MT41J128M16JT-125 */
  86 static struct mx6_ddr3_cfg mt41j128m16jt_125 = {
  87         .mem_speed = 1600,
  88         .density = 2,
  89         .width = 16,
  90         .banks = 8,
  91         .rowaddr = 14,
  92         .coladdr = 10,
  93         .pagesz = 2,
  94         .trcd = 1375,
  95         .trcmin = 4875,
  96         .trasmin = 3500,
  97 };
  98
  99 static struct mx6_mmdc_calibration mx6dq_mmdc_calib = {
 100         /* Write leveling calibration determine */
 101         .p0_mpwldectrl0 = 0x001f001f,
 102         .p0_mpwldectrl1 = 0x001f001f,
 103         .p1_mpwldectrl0 = 0x00440044,
 104         .p1_mpwldectrl1 = 0x00440044,
 105         /* Read DQS Gating calibration */
 106         .p0_mpdgctrl0 = 0x434b0350,
 107         .p0_mpdgctrl1 = 0x034c0359,
 108         .p1_mpdgctrl0 = 0x434b0350,
 109         .p1_mpdgctrl1 = 0x03650348,
 110         /* Read Calibration: DQS delay relative to DQ read access */
 111         .p0_mprddlctl = 0x4436383b,
 112         .p1_mprddlctl = 0x39393341,
 113         /* Write Calibration: DQ/DM delay relative to DQS write access */
 114         .p0_mpwrdlctl = 0x35373933,
 115         .p1_mpwrdlctl = 0x48254a36,
 116 };
 117
 118 static void spl_dram_init(int width)
 119 {
 120         struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125;
 121         struct mx6_ddr_sysinfo sysinfo = {
 122                 /* width of data bus:0=16,1=32,2=64 */
 123                 .dsize = width / 32,
 124                 /* config for full 4GB range so that get_mem_size() works */
 125                 .cs_density = 32, /* 32Gb per CS */
 126                 /* single chip select */
 127                 .ncs = 1,
 128                 .cs1_mirror = 1,
 129                 .rtt_wr = 1 /*DDR3_RTT_60_OHM*/,        /* RTT_Wr = RZQ/4 */
 130 #ifdef RTT_NOM_120OHM
 131                 .rtt_nom = 2 /*DDR3_RTT_120_OHM*/,      /* RTT_Nom = RZQ/2 */
 132 #else
 133                 .rtt_nom = 1 /*DDR3_RTT_60_OHM*/,       /* RTT_Nom = RZQ/4 */
 134 #endif
 135                 .walat = 0,     /* Write additional latency */
 136                 .ralat = 5,     /* Read additional latency */
 137                 .mif3_mode = 3, /* Command prediction working mode */
 138                 .bi_on = 1,     /* Bank interleaving enabled */
 139                 .sde_to_rst = 0x10,     /* 14 cycles, 200us (JEDEC default) */
 140                 .rst_to_cke = 0x23,     /* 33 cycles, 500us (JEDEC default) */
 141                 .ddr_type = DDR_TYPE_DDR3,
 142                 .refsel = 1,            /* Refresh cycles at 32KHz */
 143                 .refr = 7,              /* 8 refresh commands per refresh cycle */
 144         };
 145
 146         mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs);
 147         mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem);
 148 }
 149
 150 /*
 151  * Called from C runtime startup code (arch/arm/lib/crt0.S:_main)
 152  * - we have a stack and a place to store GD, both in SRAM
 153  * - no variable global data is available
 154  */
 155 void board_init_f(ulong dummy)
 156 {
 157         /* Setup AIPS and disable watchdog */
 158         arch_cpu_init();
 159
 160         ccgr_init();
 161         gpr_init();
 162
 163         /* UART iomux */
 164         board_early_init_f();
 165
 166         /* Setup GP timer */
 167         timer_init();
 168
 169         /* UART clocks enabled and gd valid - init serial console */
 170         preloader_console_init();
 171
 172         /* Init DDR with 32bit width */
 173         spl_dram_init(32);
 174
 175         /* Clear the BSS */
 176         memset(__bss_start, 0, __bss_end - __bss_start);
 177
 178         /*
 179          * Setup enet related MUXing early to give the PHY
 180          * some time to wake-up from reset
 181          */
 182         platinum_setup_enet();
 183
 184         /* load/boot image from boot device */
 185         board_init_r(NULL, 0);
 186 }