board/barco/platinum/platinum.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2014, Barco (www.barco.com)
   4  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   5  */
   6
   7 #include <common.h>
   8 #include <init.h>
   9 #include <mmc.h>
  10 #include <fsl_esdhc_imx.h>
  11 #include <miiphy.h>
  12 #include <net.h>
  13 #include <netdev.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/imx-regs.h>
  17 #include <asm/arch/iomux.h>
  18 #include <asm/arch/mx6-pins.h>
  19 #include <asm/arch/crm_regs.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <asm/gpio.h>
  22 #include <asm/mach-imx/iomux-v3.h>
  23 #include <asm/mach-imx/boot_mode.h>
  24
  25 #include "platinum.h"
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 iomux_v3_cfg_t const usdhc3_pads[] = {
  30         MX6_PAD_SD3_CLK__SD3_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  31         MX6_PAD_SD3_CMD__SD3_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  32         MX6_PAD_SD3_DAT0__SD3_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  33         MX6_PAD_SD3_DAT1__SD3_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  34         MX6_PAD_SD3_DAT2__SD3_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  35         MX6_PAD_SD3_DAT3__SD3_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  36         MX6_PAD_SD3_DAT5__GPIO7_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  37 };
  38
  39 iomux_v3_cfg_t nfc_pads[] = {
  40         MX6_PAD_NANDF_CLE__NAND_CLE             | MUX_PAD_CTRL(NO_PAD_CTRL),
  41         MX6_PAD_NANDF_ALE__NAND_ALE             | MUX_PAD_CTRL(NO_PAD_CTRL),
  42         MX6_PAD_NANDF_WP_B__NAND_WP_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
  43         MX6_PAD_NANDF_RB0__NAND_READY_B         | MUX_PAD_CTRL(NO_PAD_CTRL),
  44         MX6_PAD_NANDF_CS0__NAND_CE0_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
  45         MX6_PAD_NANDF_CS1__NAND_CE1_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
  46         MX6_PAD_NANDF_CS2__NAND_CE2_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
  47         MX6_PAD_NANDF_CS3__NAND_CE3_B           | MUX_PAD_CTRL(NO_PAD_CTRL),
  48         MX6_PAD_SD4_CMD__NAND_RE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
  49         MX6_PAD_SD4_CLK__NAND_WE_B              | MUX_PAD_CTRL(NO_PAD_CTRL),
  50         MX6_PAD_NANDF_D0__NAND_DATA00           | MUX_PAD_CTRL(NO_PAD_CTRL),
  51         MX6_PAD_NANDF_D1__NAND_DATA01           | MUX_PAD_CTRL(NO_PAD_CTRL),
  52         MX6_PAD_NANDF_D2__NAND_DATA02           | MUX_PAD_CTRL(NO_PAD_CTRL),
  53         MX6_PAD_NANDF_D3__NAND_DATA03           | MUX_PAD_CTRL(NO_PAD_CTRL),
  54         MX6_PAD_NANDF_D4__NAND_DATA04           | MUX_PAD_CTRL(NO_PAD_CTRL),
  55         MX6_PAD_NANDF_D5__NAND_DATA05           | MUX_PAD_CTRL(NO_PAD_CTRL),
  56         MX6_PAD_NANDF_D6__NAND_DATA06           | MUX_PAD_CTRL(NO_PAD_CTRL),
  57         MX6_PAD_NANDF_D7__NAND_DATA07           | MUX_PAD_CTRL(NO_PAD_CTRL),
  58         MX6_PAD_SD4_DAT0__NAND_DQS              | MUX_PAD_CTRL(NO_PAD_CTRL),
  59 };
  60
  61 struct fsl_esdhc_cfg usdhc_cfg[] = {
  62         { USDHC3_BASE_ADDR },
  63 };
  64
  65 void setup_gpmi_nand(void)
  66 {
  67         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68
  69         /* config gpmi nand iomux */
  70         imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
  71
  72         /* config gpmi and bch clock to 100 MHz */
  73         clrsetbits_le32(&mxc_ccm->cs2cdr,
  74                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
  75                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
  76                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
  77                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
  78                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
  79                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
  80
  81         /* enable gpmi and bch clock gating */
  82         setbits_le32(&mxc_ccm->CCGR4,
  83                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
  84                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
  85                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
  86                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
  87                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
  88
  89         /* enable apbh clock gating */
  90         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
  91 }
  92
  93 int dram_init(void)
  94 {
  95         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  96
  97         return 0;
  98 }
  99
 100 int board_ehci_hcd_init(int port)
 101 {
 102         return 0;
 103 }
 104
 105 int board_mmc_getcd(struct mmc *mmc)
 106 {
 107         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 108
 109         if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) {
 110                 unsigned sd3_cd = IMX_GPIO_NR(7, 0);
 111                 gpio_direction_input(sd3_cd);
 112                 return !gpio_get_value(sd3_cd);
 113         }
 114
 115         return 0;
 116 }
 117
 118 int board_mmc_init(bd_t *bis)
 119 {
 120         imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 121         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 122
 123         return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 124 }
 125
 126 void board_init_gpio(void)
 127 {
 128         platinum_init_gpio();
 129 }
 130
 131 void board_init_gpmi_nand(void)
 132 {
 133         setup_gpmi_nand();
 134 }
 135
 136 void board_init_i2c(void)
 137 {
 138         platinum_setup_i2c();
 139 }
 140
 141 void board_init_spi(void)
 142 {
 143         platinum_setup_spi();
 144 }
 145
 146 void board_init_uart(void)
 147 {
 148         platinum_setup_uart();
 149 }
 150
 151 void board_init_usb(void)
 152 {
 153         platinum_init_usb();
 154 }
 155
 156 void board_init_finished(void)
 157 {
 158         platinum_init_finished();
 159 }
 160
 161 int board_phy_config(struct phy_device *phydev)
 162 {
 163         return platinum_phy_config(phydev);
 164 }
 165
 166 int board_eth_init(bd_t *bis)
 167 {
 168         return cpu_eth_init(bis);
 169 }
 170
 171 int board_early_init_f(void)
 172 {
 173         board_init_uart();
 174
 175         return 0;
 176 }
 177
 178 int board_init(void)
 179 {
 180         /* address of boot parameters */
 181         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 182
 183         board_init_spi();
 184
 185         board_init_i2c();
 186
 187         board_init_gpmi_nand();
 188
 189         board_init_gpio();
 190
 191         board_init_usb();
 192
 193         board_init_finished();
 194
 195         return 0;
 196 }
 197
 198 int checkboard(void)
 199 {
 200         puts("Board: " CONFIG_PLATINUM_BOARD "\n");
 201         return 0;
 202 }
 203
 204 static const struct boot_mode board_boot_modes[] = {
 205         /* NAND */
 206         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
 207         /* 4 bit bus width */
 208         { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) },
 209         { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) },
 210         { NULL, 0 },
 211 };
 212
 213 int misc_init_r(void)
 214 {
 215         add_board_boot_modes(board_boot_modes);
 216
 217         return 0;
 218 }