board/atmel/sama5d2_xplained/sama5d2_xplained.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Atmel Corporation
   4  *                    Wenyou.Yang <wenyou.yang@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <init.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91_common.h>
  12 #include <asm/arch/atmel_pio4.h>
  13 #include <asm/arch/atmel_mpddrc.h>
  14 #include <asm/arch/atmel_sdhci.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/sama5d2.h>
  18
  19 extern void at91_pda_detect(void);
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 static void board_usb_hw_init(void)
  24 {
  25         atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
  26 }
  27
  28 #ifdef CONFIG_BOARD_LATE_INIT
  29 int board_late_init(void)
  30 {
  31 #ifdef CONFIG_DM_VIDEO
  32         at91_video_show_board_info();
  33 #endif
  34         at91_pda_detect();
  35         return 0;
  36 }
  37 #endif
  38
  39 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  40 static void board_uart1_hw_init(void)
  41 {
  42         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);        /* URXD1 */
  43         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
  44
  45         at91_periph_clk_enable(ATMEL_ID_UART1);
  46 }
  47
  48 void board_debug_uart_init(void)
  49 {
  50         board_uart1_hw_init();
  51 }
  52 #endif
  53
  54 #ifdef CONFIG_BOARD_EARLY_INIT_F
  55 int board_early_init_f(void)
  56 {
  57 #ifdef CONFIG_DEBUG_UART
  58         debug_uart_init();
  59 #endif
  60
  61         return 0;
  62 }
  63 #endif
  64
  65 int board_init(void)
  66 {
  67         /* address of boot parameters */
  68         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  69
  70 #ifdef CONFIG_CMD_USB
  71         board_usb_hw_init();
  72 #endif
  73
  74         return 0;
  75 }
  76
  77 int dram_init(void)
  78 {
  79         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  80                                     CONFIG_SYS_SDRAM_SIZE);
  81         return 0;
  82 }
  83
  84 #define AT24MAC_MAC_OFFSET      0x9a
  85
  86 #ifdef CONFIG_MISC_INIT_R
  87 int misc_init_r(void)
  88 {
  89 #ifdef CONFIG_I2C_EEPROM
  90         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
  91 #endif
  92
  93         return 0;
  94 }
  95 #endif
  96
  97 /* SPL */
  98 #ifdef CONFIG_SPL_BUILD
  99 void spl_board_init(void)
 100 {
 101 }
 102
 103 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 104 {
 105         ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
 106
 107         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 108                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 109                     ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
 110                     ATMEL_MPDDRC_CR_DIC_DS |
 111                     ATMEL_MPDDRC_CR_DIS_DLL |
 112                     ATMEL_MPDDRC_CR_NB_8BANKS |
 113                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 114                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 115
 116         ddrc->rtr = 0x511;
 117
 118         ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 119                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 120                       4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 121                       9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 122                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 123                       4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 124                       4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 125                       4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 126
 127         ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
 128                       29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 129                       0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 130                       3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
 131
 132         ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
 133                       0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 134                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 135                       4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 136                       7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
 137 }
 138
 139 void mem_init(void)
 140 {
 141         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 142         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 143         struct atmel_mpddrc_config ddrc_config;
 144         u32 reg;
 145
 146         ddrc_conf(&ddrc_config);
 147
 148         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 149         writel(AT91_PMC_DDR, &pmc->scer);
 150
 151         reg = readl(&mpddrc->io_calibr);
 152         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 153         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 154         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 155         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
 156         writel(reg, &mpddrc->io_calibr);
 157
 158         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
 159                &mpddrc->rd_data_path);
 160
 161         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 162
 163         writel(0x3, &mpddrc->cal_mr4);
 164         writel(64, &mpddrc->tim_cal);
 165 }
 166
 167 void at91_pmc_init(void)
 168 {
 169         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 170         u32 tmp;
 171
 172         /*
 173          * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 174          * so we need to slow down and configure MCKR accordingly.
 175          * This is why we have a special flavor of the switching function.
 176          */
 177         tmp = AT91_PMC_MCKR_PLLADIV_2 |
 178               AT91_PMC_MCKR_MDIV_3 |
 179               AT91_PMC_MCKR_CSS_MAIN;
 180         at91_mck_init_down(tmp);
 181
 182         tmp = AT91_PMC_PLLAR_29 |
 183               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 184               AT91_PMC_PLLXR_MUL(82) |
 185               AT91_PMC_PLLXR_DIV(1);
 186         at91_plla_init(tmp);
 187
 188         writel(0x0 << 8, &pmc->pllicpr);
 189
 190         tmp = AT91_PMC_MCKR_H32MXDIV |
 191               AT91_PMC_MCKR_PLLADIV_2 |
 192               AT91_PMC_MCKR_MDIV_3 |
 193               AT91_PMC_MCKR_CSS_PLLA;
 194         at91_mck_init(tmp);
 195 }
 196 #endif