board/atmel/sama5d2_xplained/sama5d2_xplained.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2015 Atmel Corporation
   4  *                    Wenyou.Yang <wenyou.yang@atmel.com>
   5  */
   6
   7 #include <common.h>
   8 #include <debug_uart.h>
   9 #include <init.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91_common.h>
  12 #include <asm/arch/atmel_pio4.h>
  13 #include <asm/arch/atmel_mpddrc.h>
  14 #include <asm/arch/atmel_sdhci.h>
  15 #include <asm/arch/clk.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/sama5d2.h>
  18
  19 extern void at91_pda_detect(void);
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #ifdef CONFIG_CMD_USB
  24 static void board_usb_hw_init(void)
  25 {
  26         atmel_pio4_set_pio_output(AT91_PIO_PORTB, 10, 1);
  27 }
  28 #endif
  29
  30 #ifdef CONFIG_BOARD_LATE_INIT
  31 int board_late_init(void)
  32 {
  33 #ifdef CONFIG_DM_VIDEO
  34         at91_video_show_board_info();
  35 #endif
  36         at91_pda_detect();
  37         return 0;
  38 }
  39 #endif
  40
  41 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
  42 static void board_uart1_hw_init(void)
  43 {
  44         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK);        /* URXD1 */
  45         atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0);  /* UTXD1 */
  46
  47         at91_periph_clk_enable(ATMEL_ID_UART1);
  48 }
  49
  50 void board_debug_uart_init(void)
  51 {
  52         board_uart1_hw_init();
  53 }
  54 #endif
  55
  56 #ifdef CONFIG_BOARD_EARLY_INIT_F
  57 int board_early_init_f(void)
  58 {
  59 #ifdef CONFIG_DEBUG_UART
  60         debug_uart_init();
  61 #endif
  62
  63         return 0;
  64 }
  65 #endif
  66
  67 int board_init(void)
  68 {
  69         /* address of boot parameters */
  70         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  71
  72 #ifdef CONFIG_CMD_USB
  73         board_usb_hw_init();
  74 #endif
  75
  76         return 0;
  77 }
  78
  79 int dram_init(void)
  80 {
  81         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  82                                     CONFIG_SYS_SDRAM_SIZE);
  83         return 0;
  84 }
  85
  86 #define AT24MAC_MAC_OFFSET      0x9a
  87
  88 #ifdef CONFIG_MISC_INIT_R
  89 int misc_init_r(void)
  90 {
  91 #ifdef CONFIG_I2C_EEPROM
  92         at91_set_ethaddr(AT24MAC_MAC_OFFSET);
  93 #endif
  94
  95         return 0;
  96 }
  97 #endif
  98
  99 /* SPL */
 100 #ifdef CONFIG_SPL_BUILD
 101 void spl_board_init(void)
 102 {
 103 }
 104
 105 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
 106 {
 107         ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
 108
 109         ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
 110                     ATMEL_MPDDRC_CR_NR_ROW_14 |
 111                     ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
 112                     ATMEL_MPDDRC_CR_DIC_DS |
 113                     ATMEL_MPDDRC_CR_DIS_DLL |
 114                     ATMEL_MPDDRC_CR_NB_8BANKS |
 115                     ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
 116                     ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
 117
 118         ddrc->rtr = 0x511;
 119
 120         ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
 121                       3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
 122                       4 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
 123                       9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
 124                       3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
 125                       4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
 126                       4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
 127                       4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
 128
 129         ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
 130                       29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
 131                       0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
 132                       3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET);
 133
 134         ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
 135                       0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
 136                       0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
 137                       4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
 138                       7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET);
 139 }
 140
 141 void mem_init(void)
 142 {
 143         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 144         struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
 145         struct atmel_mpddrc_config ddrc_config;
 146         u32 reg;
 147
 148         ddrc_conf(&ddrc_config);
 149
 150         at91_periph_clk_enable(ATMEL_ID_MPDDRC);
 151         writel(AT91_PMC_DDR, &pmc->scer);
 152
 153         reg = readl(&mpddrc->io_calibr);
 154         reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
 155         reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
 156         reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
 157         reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
 158         writel(reg, &mpddrc->io_calibr);
 159
 160         writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_TWO_CYCLE,
 161                &mpddrc->rd_data_path);
 162
 163         ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
 164
 165         writel(0x3, &mpddrc->cal_mr4);
 166         writel(64, &mpddrc->tim_cal);
 167 }
 168
 169 void at91_pmc_init(void)
 170 {
 171         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 172         u32 tmp;
 173
 174         /*
 175          * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
 176          * so we need to slow down and configure MCKR accordingly.
 177          * This is why we have a special flavor of the switching function.
 178          */
 179         tmp = AT91_PMC_MCKR_PLLADIV_2 |
 180               AT91_PMC_MCKR_MDIV_3 |
 181               AT91_PMC_MCKR_CSS_MAIN;
 182         at91_mck_init_down(tmp);
 183
 184         tmp = AT91_PMC_PLLAR_29 |
 185               AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
 186               AT91_PMC_PLLXR_MUL(82) |
 187               AT91_PMC_PLLXR_DIV(1);
 188         at91_plla_init(tmp);
 189
 190         writel(0x0 << 8, &pmc->pllicpr);
 191
 192         tmp = AT91_PMC_MCKR_H32MXDIV |
 193               AT91_PMC_MCKR_PLLADIV_2 |
 194               AT91_PMC_MCKR_MDIV_3 |
 195               AT91_PMC_MCKR_CSS_PLLA;
 196         at91_mck_init(tmp);
 197 }
 198 #endif