1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Microchip Corporation
4 * Wenyou Yang <wenyou.yang@microchip.com>
8 #include <debug_uart.h>
15 #include <asm/arch/at91_common.h>
16 #include <asm/arch/atmel_pio4.h>
17 #include <asm/arch/atmel_mpddrc.h>
18 #include <asm/arch/atmel_sdhci.h>
19 #include <asm/arch/clk.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/sama5d2.h>
22 #include <asm/arch/sama5d2_smc.h>
24 extern void at91_pda_detect(void);
26 DECLARE_GLOBAL_DATA_PTR;
28 #ifdef CONFIG_NAND_ATMEL
29 static void board_nand_hw_init(void)
31 struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
33 at91_periph_clk_enable(ATMEL_ID_HSMC);
35 /* Configure SMC CS3 for NAND */
36 writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
37 AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1),
39 writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(4) |
40 AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3),
42 writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(5),
44 writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) |
45 AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) |
46 AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3) |
47 AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings);
48 writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
49 AT91_SMC_MODE_EXNW_DISABLE |
51 AT91_SMC_MODE_TDF_CYCLE(3),
54 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 22, ATMEL_PIO_DRVSTR_ME); /* D0 */
55 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 23, ATMEL_PIO_DRVSTR_ME); /* D1 */
56 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 24, ATMEL_PIO_DRVSTR_ME); /* D2 */
57 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 25, ATMEL_PIO_DRVSTR_ME); /* D3 */
58 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 26, ATMEL_PIO_DRVSTR_ME); /* D4 */
59 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 27, ATMEL_PIO_DRVSTR_ME); /* D5 */
60 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 28, ATMEL_PIO_DRVSTR_ME); /* D6 */
61 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 29, ATMEL_PIO_DRVSTR_ME); /* D7 */
62 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 2, 0); /* RE */
63 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 30, 0); /* WE */
64 atmel_pio4_set_b_periph(AT91_PIO_PORTA, 31, ATMEL_PIO_PUEN_MASK); /* NCS */
65 atmel_pio4_set_b_periph(AT91_PIO_PORTC, 8, ATMEL_PIO_PUEN_MASK); /* RDY */
66 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 0, ATMEL_PIO_PUEN_MASK); /* ALE */
67 atmel_pio4_set_b_periph(AT91_PIO_PORTB, 1, ATMEL_PIO_PUEN_MASK); /* CLE */
71 #ifdef CONFIG_BOARD_LATE_INIT
72 int board_late_init(void)
79 static void board_usb_hw_init(void)
81 atmel_pio4_set_pio_output(AT91_PIO_PORTB, 12, ATMEL_PIO_PUEN_MASK);
84 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
85 static void board_uart0_hw_init(void)
87 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
88 atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0); /* UTXD0 */
90 at91_periph_clk_enable(ATMEL_ID_UART0);
93 void board_debug_uart_init(void)
95 board_uart0_hw_init();
99 #ifdef CONFIG_BOARD_EARLY_INIT_F
100 int board_early_init_f(void)
102 #ifdef CONFIG_DEBUG_UART
111 /* address of boot parameters */
112 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
114 #ifdef CONFIG_NAND_ATMEL
115 board_nand_hw_init();
117 #ifdef CONFIG_CMD_USB
125 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
126 CONFIG_SYS_SDRAM_SIZE);
130 #define AT24MAC_MAC_OFFSET 0xfa
132 #ifdef CONFIG_MISC_INIT_R
133 int misc_init_r(void)
135 #ifdef CONFIG_I2C_EEPROM
136 at91_set_ethaddr(AT24MAC_MAC_OFFSET);