1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017 Microchip Corporation
4 * Wenyou.Yang <wenyou.yang@microchip.com>
8 #include <debug_uart.h>
11 #include <asm/arch/at91_common.h>
12 #include <asm/arch/atmel_pio4.h>
13 #include <asm/arch/atmel_mpddrc.h>
14 #include <asm/arch/atmel_sdhci.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/sama5d2.h>
19 extern void at91_pda_detect(void);
21 DECLARE_GLOBAL_DATA_PTR;
24 static void board_usb_hw_init(void)
26 atmel_pio4_set_pio_output(AT91_PIO_PORTA, 27, 1);
30 #ifdef CONFIG_BOARD_LATE_INIT
31 int board_late_init(void)
33 #ifdef CONFIG_DM_VIDEO
34 at91_video_show_board_info();
41 #ifdef CONFIG_DEBUG_UART_BOARD_INIT
42 static void board_uart1_hw_init(void)
44 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 2, ATMEL_PIO_PUEN_MASK); /* URXD1 */
45 atmel_pio4_set_a_periph(AT91_PIO_PORTD, 3, 0); /* UTXD1 */
47 at91_periph_clk_enable(ATMEL_ID_UART1);
50 void board_debug_uart_init(void)
52 board_uart1_hw_init();
56 #ifdef CONFIG_BOARD_EARLY_INIT_F
57 int board_early_init_f(void)
59 #ifdef CONFIG_DEBUG_UART
69 /* address of boot parameters */
70 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
81 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
82 CONFIG_SYS_SDRAM_SIZE);
86 #define MAC24AA_MAC_OFFSET 0xfa
88 #ifdef CONFIG_MISC_INIT_R
91 #ifdef CONFIG_I2C_EEPROM
92 at91_set_ethaddr(MAC24AA_MAC_OFFSET);
99 #ifdef CONFIG_SPL_BUILD
100 void spl_board_init(void)
104 static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
106 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
108 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
109 ATMEL_MPDDRC_CR_NR_ROW_13 |
110 ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
111 ATMEL_MPDDRC_CR_DIC_DS |
112 ATMEL_MPDDRC_CR_ZQ_LONG |
113 ATMEL_MPDDRC_CR_NB_8BANKS |
114 ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
115 ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
119 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
120 (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
121 (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
122 (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
123 (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
124 (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
125 (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
126 (2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
128 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
129 (23 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
130 (200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
131 (3 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
133 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
134 (8 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
135 (4 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
136 (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
137 (8 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
142 struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
143 struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
144 struct atmel_mpddrc_config ddrc_config;
147 ddrc_conf(&ddrc_config);
149 at91_periph_clk_enable(ATMEL_ID_MPDDRC);
150 writel(AT91_PMC_DDR, &pmc->scer);
152 reg = readl(&mpddrc->io_calibr);
153 reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
154 reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
155 reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
156 reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(101);
157 writel(reg, &mpddrc->io_calibr);
159 writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
160 &mpddrc->rd_data_path);
162 ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
164 writel(0x3, &mpddrc->cal_mr4);
165 writel(64, &mpddrc->tim_cal);
168 void at91_pmc_init(void)
173 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
174 * so we need to slow down and configure MCKR accordingly.
175 * This is why we have a special flavor of the switching function.
177 tmp = AT91_PMC_MCKR_PLLADIV_2 |
178 AT91_PMC_MCKR_MDIV_3 |
179 AT91_PMC_MCKR_CSS_MAIN;
180 at91_mck_init_down(tmp);
182 tmp = AT91_PMC_PLLAR_29 |
183 AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
184 AT91_PMC_PLLXR_MUL(40) |
185 AT91_PMC_PLLXR_DIV(1);
188 tmp = AT91_PMC_MCKR_H32MXDIV |
189 AT91_PMC_MCKR_PLLADIV_2 |
190 AT91_PMC_MCKR_MDIV_3 |
191 AT91_PMC_MCKR_CSS_PLLA;