1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2002-2013
4 * Eric Jarrige <eric.jarrige@armadeus.org>
6 * based on the files by
7 * Rich Ireland, Enterasys Networks, rireland@enterasys.com
9 * Keith Outwater, keith_outwater@mvis.com
13 #include <linux/delay.h>
15 #include <asm/arch/imx-regs.h>
25 * Note that these are pointers to code that is in Flash. They will be
26 * relocated at runtime.
27 * Spartan2 code is used to download our Spartan 3 :) code is compatible.
28 * Just take care about the file size
30 xilinx_spartan3_slave_parallel_fns fpga_fns = {
46 xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
57 * Initialize GPIO port B before download
59 int fpga_pre_fn(int cookie)
61 /* Initialize GPIO pins */
62 gpio_set_value(ACFG_FPGA_PWR, 1);
63 imx_gpio_mode(ACFG_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
64 imx_gpio_mode(ACFG_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
65 imx_gpio_mode(ACFG_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
66 imx_gpio_mode(ACFG_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
67 imx_gpio_mode(ACFG_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
68 imx_gpio_mode(ACFG_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
69 imx_gpio_mode(ACFG_FPGA_SUSPEND|GPIO_OUT|GPIO_PUEN|GPIO_GPIO);
70 gpio_set_value(ACFG_FPGA_RESET, 1);
71 imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
72 imx_gpio_mode(ACFG_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
73 gpio_set_value(ACFG_FPGA_PRG, 1);
74 gpio_set_value(ACFG_FPGA_CLK, 1);
75 gpio_set_value(ACFG_FPGA_RW, 1);
76 gpio_set_value(ACFG_FPGA_CS, 1);
77 gpio_set_value(ACFG_FPGA_SUSPEND, 0);
78 gpio_set_value(ACFG_FPGA_PWR, 0);
79 udelay(30000); /*wait until supply started*/
85 * Set the FPGA's active-low program line to the specified level
87 int fpga_pgm_fn(int assert, int flush, int cookie)
89 debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
90 assert ? "high" : "low");
91 gpio_set_value(ACFG_FPGA_PRG, !assert);
96 * Set the FPGA's active-high clock line to the specified level
98 int fpga_clk_fn(int assert_clk, int flush, int cookie)
100 debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
101 assert_clk ? "high" : "low");
102 gpio_set_value(ACFG_FPGA_CLK, !assert_clk);
107 * Test the state of the active-low FPGA INIT line. Return 1 on INIT
110 int fpga_init_fn(int cookie)
113 debug("%s:%d: INIT check... ", __func__, __LINE__);
114 value = gpio_get_value(ACFG_FPGA_INIT);
115 /* printf("init value read %x",value); */
116 #ifdef CONFIG_SYS_FPGA_IS_PROTO
124 * Test the state of the active-high FPGA DONE pin
126 int fpga_done_fn(int cookie)
128 debug("%s:%d: DONE check... %s", __func__, __LINE__,
129 gpio_get_value(ACFG_FPGA_DONE) ? "high" : "low");
130 return gpio_get_value(ACFG_FPGA_DONE) ? FPGA_SUCCESS : FPGA_FAIL;
134 * Set the FPGA's wr line to the specified level
136 int fpga_wr_fn(int assert_write, int flush, int cookie)
138 debug("%s:%d: FPGA RW... %s ", __func__, __LINE__,
139 assert_write ? "high" : "low");
140 gpio_set_value(ACFG_FPGA_RW, !assert_write);
144 int fpga_cs_fn(int assert_cs, int flush, int cookie)
146 debug("%s:%d: FPGA CS %s ", __func__, __LINE__,
147 assert_cs ? "high" : "low");
148 gpio_set_value(ACFG_FPGA_CS, !assert_cs);
152 int fpga_rdata_fn(unsigned char *data, int cookie)
154 debug("%s:%d: FPGA READ DATA %02X ", __func__, __LINE__,
155 *((char *)ACFG_FPGA_RDATA));
156 *data = (unsigned char)
157 ((*((unsigned short *)ACFG_FPGA_RDATA))&0x00FF);
161 int fpga_wdata_fn(unsigned char data, int flush, int cookie)
163 debug("%s:%d: FPGA WRITE DATA %02X ", __func__, __LINE__,
165 *((unsigned short *)ACFG_FPGA_WDATA) = data;
169 int fpga_abort_fn(int cookie)
171 return fpga_post_fn(cookie);
175 int fpga_busy_fn(int cookie)
180 int fpga_post_fn(int cookie)
182 debug("%s:%d: FPGA POST ", __func__, __LINE__);
184 imx_gpio_mode(ACFG_FPGA_RW | GPIO_PF | GPIO_PUEN);
185 imx_gpio_mode(ACFG_FPGA_CS | GPIO_PF | GPIO_PUEN);
186 imx_gpio_mode(ACFG_FPGA_CLK | GPIO_PF | GPIO_PUEN);
187 gpio_set_value(ACFG_FPGA_PRG, 1);
188 gpio_set_value(ACFG_FPGA_RESET, 0);
189 imx_gpio_mode(ACFG_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
193 void apf27_fpga_setup(void)
195 struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
196 struct system_control_regs *system =
197 (struct system_control_regs *)IMX_SYSTEM_CTL_BASE;
199 /* Configure FPGA CLKO */
200 writel(ACFG_CCSR_VAL, &pll->ccsr);
202 /* Configure strentgh for FPGA */
203 writel(ACFG_DSCR10_VAL, &system->dscr10);
204 writel(ACFG_DSCR3_VAL, &system->dscr3);
205 writel(ACFG_DSCR7_VAL, &system->dscr7);
206 writel(ACFG_DSCR2_VAL, &system->dscr2);
210 * Initialize the fpga. Return 1 on success, 0 on failure.
212 void APF27_init_fpga(void)
220 for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
221 debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
222 fpga_add(fpga_xilinx, &fpga[i]);