board/Seagate/goflexhome/goflexhome.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
   4  *
   5  * Based on dockstar.c originally written by
   6  * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
   7  *
   8  * Based on sheevaplug.c originally written by
   9  * Prafulla Wadaskar <prafulla@marvell.com>
  10  * (C) Copyright 2009
  11  * Marvell Semiconductor <www.marvell.com>
  12  */
  13
  14 #include <common.h>
  15 #include <bootstage.h>
  16 #include <init.h>
  17 #include <miiphy.h>
  18 #include <net.h>
  19 #include <asm/mach-types.h>
  20 #include <asm/arch/soc.h>
  21 #include <asm/arch/mpp.h>
  22 #include <asm/arch/cpu.h>
  23 #include <asm/io.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 int board_early_init_f(void)
  28 {
  29         /* Multi-Purpose Pins Functionality configuration */
  30         static const u32 kwmpp_config[] = {
  31                 MPP0_NF_IO2,
  32                 MPP1_NF_IO3,
  33                 MPP2_NF_IO4,
  34                 MPP3_NF_IO5,
  35                 MPP4_NF_IO6,
  36                 MPP5_NF_IO7,
  37                 MPP6_SYSRST_OUTn,
  38                 MPP7_GPO,
  39                 MPP8_UART0_RTS,
  40                 MPP9_UART0_CTS,
  41                 MPP10_UART0_TXD,
  42                 MPP11_UART0_RXD,
  43                 MPP12_SD_CLK,
  44                 MPP13_SD_CMD,
  45                 MPP14_SD_D0,
  46                 MPP15_SD_D1,
  47                 MPP16_SD_D2,
  48                 MPP17_SD_D3,
  49                 MPP18_NF_IO0,
  50                 MPP19_NF_IO1,
  51                 MPP20_GPIO,
  52                 MPP21_GPIO,
  53                 MPP22_GPIO,
  54                 MPP23_GPIO,
  55                 MPP24_GPIO,
  56                 MPP25_GPIO,
  57                 MPP26_GPIO,
  58                 MPP27_GPIO,
  59                 MPP28_GPIO,
  60                 MPP29_TSMP9,
  61                 MPP30_GPIO,
  62                 MPP31_GPIO,
  63                 MPP32_GPIO,
  64                 MPP33_GPIO,
  65                 MPP34_GPIO,
  66                 MPP35_GPIO,
  67                 MPP36_GPIO,
  68                 MPP37_GPIO,
  69                 MPP38_GPIO,
  70                 MPP39_GPIO,
  71                 MPP40_GPIO,
  72                 MPP41_GPIO,
  73                 MPP42_GPIO,
  74                 MPP43_GPIO,
  75                 MPP44_GPIO,
  76                 MPP45_GPIO,
  77                 MPP46_GPIO,
  78                 MPP47_GPIO,
  79                 MPP48_GPIO,
  80                 MPP49_GPIO,
  81                 0
  82         };
  83
  84         /*
  85          * default gpio configuration
  86          * There are maximum 64 gpios controlled through 2 sets of registers
  87          * the  below configuration configures mainly initial LED status
  88          */
  89         mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
  90                           GOFLEXHOME_OE_VAL_HIGH,
  91                           GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
  92         kirkwood_mpp_conf(kwmpp_config, NULL);
  93         return 0;
  94 }
  95
  96 int board_init(void)
  97 {
  98         /*
  99          * arch number of board
 100          */
 101         gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
 102
 103         /* address of boot parameters */
 104         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
 105
 106         return 0;
 107 }
 108
 109 #ifdef CONFIG_RESET_PHY_R
 110 /* Configure and enable MV88E1116 PHY */
 111 void reset_phy(void)
 112 {
 113         u16 reg;
 114         u16 devadr;
 115         char *name = "egiga0";
 116
 117         if (miiphy_set_current_dev(name))
 118                 return;
 119
 120         /* command to read PHY dev address */
 121         if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
 122                 printf("Err..%s could not read PHY dev address\n",
 123                        __func__);
 124                 return;
 125         }
 126
 127         /*
 128          * Enable RGMII delay on Tx and Rx for CPU port
 129          * Ref: sec 4.7.2 of chip datasheet
 130          */
 131         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
 132         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
 133         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
 134         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
 135         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
 136
 137         /* reset the phy */
 138         miiphy_reset(name, devadr);
 139
 140         printf("88E1116 Initialized on %s\n", name);
 141 }
 142 #endif /* CONFIG_RESET_PHY_R */
 143
 144 #define GREEN_LED       (1 << 14)
 145 #define ORANGE_LED      (1 << 15)
 146 #define BOTH_LEDS       (GREEN_LED | ORANGE_LED)
 147 #define NEITHER_LED     0
 148
 149 static void set_leds(u32 leds, u32 blinking)
 150 {
 151         struct kwgpio_registers *r;
 152         u32 oe;
 153         u32 bl;
 154
 155         r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
 156         oe = readl(&r->oe) | BOTH_LEDS;
 157         writel(oe & ~leds, &r->oe);     /* active low */
 158         bl = readl(&r->blink_en) & ~BOTH_LEDS;
 159         writel(bl | blinking, &r->blink_en);
 160 }
 161
 162 void show_boot_progress(int val)
 163 {
 164         switch (val) {
 165         case BOOTSTAGE_ID_RUN_OS:               /* booting Linux */
 166                 set_leds(BOTH_LEDS, NEITHER_LED);
 167                 break;
 168         case BOOTSTAGE_ID_NET_ETH_START:        /* Ethernet initialization */
 169                 set_leds(GREEN_LED, GREEN_LED);
 170                 break;
 171         default:
 172                 if (val < 0)    /* error */
 173                         set_leds(ORANGE_LED, ORANGE_LED);
 174                 break;
 175         }
 176 }