1 // SPDX-License-Identifier: GPL-2.0+
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
12 #include <asm/mach-types.h>
13 #include <asm/arch/cpu.h>
14 #include <asm/arch/soc.h>
15 #include <asm/arch/mpp.h>
16 #include "sheevaplug.h"
18 DECLARE_GLOBAL_DATA_PTR;
20 int board_early_init_f(void)
23 * default gpio configuration
24 * There are maximum 64 gpios controlled through 2 sets of registers
25 * the below configuration configures mainly initial LED status
27 mvebu_config_gpio(SHEEVAPLUG_OE_VAL_LOW,
28 SHEEVAPLUG_OE_VAL_HIGH,
29 SHEEVAPLUG_OE_LOW, SHEEVAPLUG_OE_HIGH);
31 /* Multi-Purpose Pins Functionality configuration */
32 static const u32 kwmpp_config[] = {
85 kirkwood_mpp_conf(kwmpp_config, NULL);
92 * arch number of board
94 gd->bd->bi_arch_number = MACH_TYPE_SHEEVAPLUG;
96 /* adress of boot parameters */
97 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
102 #ifdef CONFIG_RESET_PHY_R
103 /* Configure and enable MV88E1116 PHY */
108 char *name = "egiga0";
110 if (miiphy_set_current_dev(name))
113 /* command to read PHY dev address */
114 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
115 printf("Err..%s could not read PHY dev address\n",
121 * Enable RGMII delay on Tx and Rx for CPU port
122 * Ref: sec 4.7.2 of chip datasheet
124 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
125 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
126 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
127 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
128 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
131 miiphy_reset(name, devadr);
133 printf("88E1116 Initialized on %s\n", name);
135 #endif /* CONFIG_RESET_PHY_R */