1 // SPDX-License-Identifier: GPL-2.0+
4 * Net Insight <www.netinsight.net>
5 * Written-by: Simon Kagstrom <simon.kagstrom@netinsight.net>
7 * Based on sheevaplug.c:
9 * Marvell Semiconductor <www.marvell.com>
10 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
17 #include <asm/mach-types.h>
18 #include <asm/arch/cpu.h>
19 #include <asm/arch/soc.h>
20 #include <asm/arch/mpp.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 int board_early_init_f(void)
28 * default gpio configuration
29 * There are maximum 64 gpios controlled through 2 sets of registers
30 * the below configuration configures mainly initial LED status
32 mvebu_config_gpio(OPENRD_OE_VAL_LOW,
34 OPENRD_OE_LOW, OPENRD_OE_HIGH);
36 /* Multi-Purpose Pins Functionality configuration */
37 static const u32 kwmpp_config[] = {
51 MPP13_SD_CMD, /* Alt UART1_TXD */
52 MPP14_SD_D0, /* Alt UART1_RXD */
72 MPP34_GPIO, /* UART1 / SD sel */
91 kirkwood_mpp_conf(kwmpp_config, NULL);
98 * arch number of board
100 #if defined(CONFIG_BOARD_IS_OPENRD_BASE)
101 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
102 #elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
103 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
104 #elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
105 gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
108 /* adress of boot parameters */
109 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
113 #ifdef CONFIG_RESET_PHY_R
114 /* Configure and enable MV88E1116/88E1121 PHY */
115 void mv_phy_init(char *name)
120 if (miiphy_set_current_dev(name))
123 /* command to read PHY dev address */
124 if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
125 printf("Err..%s could not read PHY dev address\n", __func__);
130 * Enable RGMII delay on Tx and Rx for CPU port
131 * Ref: sec 4.7.2 of chip datasheet
133 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
134 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, ®);
135 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
136 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
137 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
140 miiphy_reset(name, devadr);
142 printf(PHY_NO" Initialized on %s\n", name);
147 mv_phy_init("egiga0");
149 #ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
150 /* Kirkwood ethernet driver is written with the assumption that in case
151 * of multiple PHYs, their addresses are consecutive. But unfortunately
152 * in case of OpenRD-Client, PHY addresses are not consecutive.*/
153 miiphy_write("egiga1", 0xEE, 0xEE, 24);
156 #if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
157 defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
158 /* configure and initialize both PHY's */
159 mv_phy_init("egiga1");
162 #endif /* CONFIG_RESET_PHY_R */