board/Marvell/guruplug/guruplug.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2009
   4  * Marvell Semiconductor <www.marvell.com>
   5  * Written-by: Siddarth Gore <gores@marvell.com>
   6  */
   7
   8 #include <common.h>
   9 #include <init.h>
  10 #include <miiphy.h>
  11 #include <net.h>
  12 #include <asm/mach-types.h>
  13 #include <asm/arch/cpu.h>
  14 #include <asm/arch/soc.h>
  15 #include <asm/arch/mpp.h>
  16 #include "guruplug.h"
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 int board_early_init_f(void)
  21 {
  22         /*
  23          * default gpio configuration
  24          * There are maximum 64 gpios controlled through 2 sets of registers
  25          * the  below configuration configures mainly initial LED status
  26          */
  27         mvebu_config_gpio(GURUPLUG_OE_VAL_LOW,
  28                           GURUPLUG_OE_VAL_HIGH,
  29                           GURUPLUG_OE_LOW, GURUPLUG_OE_HIGH);
  30
  31         /* Multi-Purpose Pins Functionality configuration */
  32         static const u32 kwmpp_config[] = {
  33                 MPP0_NF_IO2,
  34                 MPP1_NF_IO3,
  35                 MPP2_NF_IO4,
  36                 MPP3_NF_IO5,
  37                 MPP4_NF_IO6,
  38                 MPP5_NF_IO7,
  39                 MPP6_SYSRST_OUTn,
  40                 MPP7_GPO,       /* GPIO_RST */
  41                 MPP8_TW_SDA,
  42                 MPP9_TW_SCK,
  43                 MPP10_UART0_TXD,
  44                 MPP11_UART0_RXD,
  45                 MPP12_SD_CLK,
  46                 MPP13_SD_CMD,
  47                 MPP14_SD_D0,
  48                 MPP15_SD_D1,
  49                 MPP16_SD_D2,
  50                 MPP17_SD_D3,
  51                 MPP18_NF_IO0,
  52                 MPP19_NF_IO1,
  53                 MPP20_GE1_0,
  54                 MPP21_GE1_1,
  55                 MPP22_GE1_2,
  56                 MPP23_GE1_3,
  57                 MPP24_GE1_4,
  58                 MPP25_GE1_5,
  59                 MPP26_GE1_6,
  60                 MPP27_GE1_7,
  61                 MPP28_GE1_8,
  62                 MPP29_GE1_9,
  63                 MPP30_GE1_10,
  64                 MPP31_GE1_11,
  65                 MPP32_GE1_12,
  66                 MPP33_GE1_13,
  67                 MPP34_GE1_14,
  68                 MPP35_GE1_15,
  69                 MPP36_GPIO,
  70                 MPP37_GPIO,
  71                 MPP38_GPIO,
  72                 MPP39_GPIO,
  73                 MPP40_TDM_SPI_SCK,
  74                 MPP41_TDM_SPI_MISO,
  75                 MPP42_TDM_SPI_MOSI,
  76                 MPP43_GPIO,
  77                 MPP44_GPIO,
  78                 MPP45_GPIO,
  79                 MPP46_GPIO,     /* M_RLED */
  80                 MPP47_GPIO,     /* M_GLED */
  81                 MPP48_GPIO,     /* B_RLED */
  82                 MPP49_GPIO,     /* B_GLED */
  83                 0
  84         };
  85         kirkwood_mpp_conf(kwmpp_config, NULL);
  86         return 0;
  87 }
  88
  89 int board_init(void)
  90 {
  91         /*
  92          * arch number of board
  93          */
  94         gd->bd->bi_arch_number = MACH_TYPE_GURUPLUG;
  95
  96         /* adress of boot parameters */
  97         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  98
  99         return 0;
 100 }
 101
 102 #ifdef CONFIG_RESET_PHY_R
 103 void mv_phy_88e1121_init(char *name)
 104 {
 105         u16 reg;
 106         u16 devadr;
 107
 108         if (miiphy_set_current_dev(name))
 109                 return;
 110
 111         /* command to read PHY dev address */
 112         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
 113                 printf("Err..%s could not read PHY dev address\n",
 114                         __FUNCTION__);
 115                 return;
 116         }
 117
 118         /*
 119          * Enable RGMII delay on Tx and Rx for CPU port
 120          * Ref: sec 4.7.2 of chip datasheet
 121          */
 122         miiphy_write(name, devadr, MV88E1121_PGADR_REG, 2);
 123         miiphy_read(name, devadr, MV88E1121_MAC_CTRL2_REG, &reg);
 124         reg |= (MV88E1121_RGMII_RXTM_CTRL | MV88E1121_RGMII_TXTM_CTRL);
 125         miiphy_write(name, devadr, MV88E1121_MAC_CTRL2_REG, reg);
 126         miiphy_write(name, devadr, MV88E1121_PGADR_REG, 0);
 127
 128         /* reset the phy */
 129         miiphy_reset(name, devadr);
 130
 131         printf("88E1121 Initialized on %s\n", name);
 132 }
 133
 134 void reset_phy(void)
 135 {
 136         /* configure and initialize both PHY's */
 137         mv_phy_88e1121_init("egiga0");
 138         mv_phy_88e1121_init("egiga1");
 139 }
 140 #endif /* CONFIG_RESET_PHY_R */