1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
8 #include <binman_sym.h>
16 #include <spi_flash.h>
17 #include <asm/intel_pinctrl.h>
18 #include <dm/uclass-internal.h>
19 #include <asm/fsp2/fsp_internal.h>
21 int arch_cpu_init_dm(void)
27 /* Make sure pads are set up early in U-Boot */
28 if (!ll_boot_init() || spl_phase() != PHASE_BOARD_F)
31 /* Probe all pinctrl devices to set up the pads */
32 ret = uclass_first_device_err(UCLASS_PINCTRL, &dev);
34 return log_msg_ret("no fsp pinctrl", ret);
35 node = ofnode_path("fsp");
36 if (!ofnode_valid(node))
37 return log_msg_ret("no fsp params", -EINVAL);
38 ret = pinctrl_config_pads_for_node(dev, node);
40 return log_msg_ret("pad config", ret);
45 #if !defined(CONFIG_TPL_BUILD)
46 binman_sym_declare(ulong, intel_fsp_m, image_pos);
47 binman_sym_declare(ulong, intel_fsp_m, size);
50 * get_cbfs_fsp() - Obtain the FSP by looking up in CBFS
52 * This looks up an FSP in a CBFS. It is used mostly for testing, when booting
53 * U-Boot from a hybrid image containing coreboot as the first-stage bootloader.
55 * The typical use for this feature is when building a Chrome OS image which
56 * includes coreboot in it. By adding U-Boot into the 'COREBOOT' CBFS as well,
57 * it is possible to make coreboot chain-load U-Boot. Thus the initial stages of
58 * the SoC init can be done by coreboot and the later stages by U-Boot. This is
59 * a convenient way to start the porting work. The jump to U-Boot can then be
60 * moved progressively earlier and earlier, until U-Boot takes over all the init
61 * and you have a native port.
63 * This function looks up a CBFS at a known location and reads the FSP-M from it
64 * so that U-Boot can init the memory.
66 * This function is not used in the normal boot but is kept here for future
69 * @type; Type to look up (only FSP_M supported at present)
70 * @map_base: Base memory address for mapped SPI
71 * @entry: Returns an entry containing the position of the FSP image
73 static int get_cbfs_fsp(enum fsp_type_t type, ulong map_base,
74 struct binman_entry *entry)
77 * Use a hard-coded position of CBFS in the ROM for now. It would be
78 * possible to read the position using the FMAP in the ROM, but since
79 * this code is only used for development, it doesn't seem worth it.
80 * Use the 'cbfstool <image> layout' command to get these values, e.g.:
81 * 'COREBOOT' (CBFS, size 1814528, offset 2117632).
83 ulong cbfs_base = 0x205000;
84 struct cbfs_priv *cbfs;
87 ret = cbfs_init_mem(map_base + cbfs_base, &cbfs);
91 const struct cbfs_cachenode *node;
93 node = cbfs_find_file(cbfs, "fspm.bin");
95 return log_msg_ret("fspm node", -ENOENT);
97 entry->image_pos = (ulong)node->data;
98 entry->size = node->data_length;
104 int fsp_locate_fsp(enum fsp_type_t type, struct binman_entry *entry,
105 bool use_spi_flash, struct udevice **devp,
106 struct fsp_header **hdrp, ulong *rom_offsetp)
108 ulong mask = CONFIG_ROM_SIZE - 1;
110 ulong rom_offset = 0;
117 * Find the devices but don't probe them, since we don't want to
118 * auto-config PCI before silicon init runs
120 ret = uclass_find_first_device(UCLASS_NORTHBRIDGE, &dev);
122 return log_msg_ret("Cannot get northbridge", ret);
123 if (!use_spi_flash) {
126 /* Just use the SPI driver to get the memory map */
127 ret = uclass_find_first_device(UCLASS_SPI_FLASH, &sf);
129 return log_msg_ret("Cannot get SPI flash", ret);
130 ret = dm_spi_get_mmap(sf, &map_base, &map_size, &offset);
132 return log_msg_ret("Could not get flash mmap", ret);
135 if (spl_phase() >= PHASE_BOARD_F) {
137 return -EPROTONOSUPPORT;
138 ret = binman_entry_find("intel-fsp-s", entry);
140 return log_msg_ret("binman entry", ret);
142 rom_offset = (map_base & mask) - CONFIG_ROM_SIZE;
147 * Support using a hybrid image build by coreboot. See
148 * the function comments for details
150 ret = get_cbfs_fsp(type, map_base, entry);
152 ulong mask = CONFIG_ROM_SIZE - 1;
155 return -EPROTONOSUPPORT;
156 entry->image_pos = binman_sym(ulong, intel_fsp_m,
158 entry->size = binman_sym(ulong, intel_fsp_m, size);
159 if (entry->image_pos != BINMAN_SYM_MISSING) {
162 entry->image_pos &= mask;
164 entry->image_pos += (map_base & mask);
171 return log_msg_ret("Cannot find FSP", ret);
172 entry->image_pos += rom_offset;
175 * Account for the time taken to read memory-mapped SPI flash since in
176 * this case we don't use the SPI driver and BOOTSTAGE_ID_ACCUM_SPI.
179 bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
180 ret = fsp_get_header(entry->image_pos, entry->size, use_spi_flash,
183 bootstage_accum(BOOTSTAGE_ID_ACCUM_MMAP_SPI);
185 return log_msg_ret("fsp_get_header", ret);
188 *rom_offsetp = rom_offset;