1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
12 #include <asm/fsp/fsp_support.h>
15 DECLARE_GLOBAL_DATA_PTR;
22 static const struct fsp_framebuffer {
27 } fsp_framebuffer_format_map[] = {
28 [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} },
29 [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} },
32 static int save_vesa_mode(struct vesa_mode_info *vesa)
34 const struct hob_graphics_info *ginfo;
35 const struct fsp_framebuffer *fbinfo;
37 ginfo = fsp_get_graphics_info(gd->arch.hob_list, NULL);
40 * If there is no graphics info structure, bail out and keep
41 * running on the serial console.
43 * Note: on some platforms (eg: Braswell), the FSP will not produce
44 * the graphics info HOB unless you plug some cables to the display
45 * interface (eg: HDMI) on the board.
48 debug("FSP graphics hand-off block not found\n");
52 vesa->x_resolution = ginfo->width;
53 vesa->y_resolution = ginfo->height;
54 vesa->bits_per_pixel = 32;
55 vesa->bytes_per_scanline = ginfo->pixels_per_scanline * 4;
56 vesa->phys_base_ptr = ginfo->fb_base;
58 if (ginfo->pixel_format >= pixel_bitmask) {
59 debug("FSP set unknown framebuffer format: %d\n",
63 fbinfo = &fsp_framebuffer_format_map[ginfo->pixel_format];
64 vesa->red_mask_size = fbinfo->red.size;
65 vesa->red_mask_pos = fbinfo->red.pos;
66 vesa->green_mask_size = fbinfo->green.size;
67 vesa->green_mask_pos = fbinfo->green.pos;
68 vesa->blue_mask_size = fbinfo->blue.size;
69 vesa->blue_mask_pos = fbinfo->blue.pos;
70 vesa->reserved_mask_size = fbinfo->rsvd.size;
71 vesa->reserved_mask_pos = fbinfo->rsvd.pos;
76 static int fsp_video_probe(struct udevice *dev)
78 struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
79 struct video_priv *uc_priv = dev_get_uclass_priv(dev);
80 struct vesa_mode_info *vesa = &mode_info.vesa;
88 /* Initialize vesa_mode_info structure */
89 ret = save_vesa_mode(vesa);
94 * The framebuffer base address in the FSP graphics info HOB reflects
95 * the value assigned by the FSP. After PCI enumeration the framebuffer
96 * base address may be relocated. Let's get the updated one from device.
98 * For IGD, it seems to be always on BAR2.
100 vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
102 ret = vbe_setup_video_priv(vesa, uc_priv, plat);
106 mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
109 printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
110 vesa->bits_per_pixel);
115 printf("No video mode configured in FSP!\n");
119 static const struct udevice_id fsp_video_ids[] = {
120 { .compatible = "fsp-fb" },
124 U_BOOT_DRIVER(fsp_video) = {
127 .of_match = fsp_video_ids,
128 .probe = fsp_video_probe,
131 static struct pci_device_id fsp_video_supported[] = {
132 { PCI_DEVICE_CLASS(PCI_CLASS_DISPLAY_VGA << 8, 0xffff00) },
136 U_BOOT_PCI_DEVICE(fsp_video, fsp_video_supported);