1 /* SPDX-License-Identifier: Intel */
3 * Copyright (c) 2019, Intel Corporation. All rights reserved.
4 * Copyright 2019 Google LLC
7 #ifndef __ASM_ARCH_FSP_M_UDP_H
8 #define __ASM_ARCH_FSP_M_UDP_H
11 #include <asm/fsp2/fsp_api.h>
13 #define FSP_DRAM_CHANNELS 4
15 struct __packed fspm_arch_upd {
21 u32 boot_loader_tolum_size;
26 struct __packed fsp_ram_channel {
38 * struct fsp_m_config - FSP-M configuration
40 * Note that headers precede this and are 64 bytes long. The hex offsets
41 * mentioned in this file are relative to the start of the header, the same
42 * convention used in Intel's APL FSP header file.
44 struct __packed fsp_m_config {
46 u32 serial_debug_port_address;
47 u8 serial_debug_port_type;
48 u8 serial_debug_port_device;
49 u8 serial_debug_port_stride_size;
52 u8 igd_dvmt50_pre_alloc;
55 u8 primary_video_adaptor;
65 u16 channel_hash_mask;
67 u8 channels_slices_enable;
68 u8 min_ref_rate2x_enable;
69 u8 dual_rank_support_enable;
71 u16 memory_size_limit;
72 u16 low_memory_max_value;
75 u16 high_memory_max_value;
79 struct fsp_ram_channel chan[FSP_DRAM_CHANNELS];
81 u16 rmt_margin_check_scale_high_threshold;
82 u8 ch_bit_swizzling[FSP_DRAM_CHANNELS][32];
84 u8 unused_upd_space0[4];
87 u8 pre_mem_gpio_table_pin_num[4];
88 u32 pre_mem_gpio_table_ptr;
89 u8 pre_mem_gpio_table_entry_num;
90 u8 enhance_port8xh_decoding;
99 void *mrc_boot_data_ptr;
104 u8 fw_trace_destination;
118 u8 periodic_retraining_disable;
119 u8 enable_reset_system;
121 u8 unused_upd_space1[3];
124 void *variable_nvs_buffer_ptr;
125 u8 reserved_fspm_upd[12];
128 /** FSP-M UPD Configuration */
129 struct __packed fspm_upd {
130 struct fsp_upd_header header;
131 struct fspm_arch_upd arch;
132 struct fsp_m_config config;
133 u8 unused_upd_space2[158];
138 #define SERIAL_DEBUG_PORT_TYPE_NONE 0
139 #define SERIAL_DEBUG_PORT_TYPE_IO 1
140 #define SERIAL_DEBUG_PORT_TYPE_MMIO 2
142 #define SERIAL_DEBUG_PORT_DEVICE_UART0 0
143 #define SERIAL_DEBUG_PORT_DEVICE_UART1 1
144 #define SERIAL_DEBUG_PORT_DEVICE_UART2 2
145 #define SERIAL_DEBUG_PORT_DEVICE_EXTERNAL 3
147 #define SERIAL_DEBUG_PORT_STRIDE_SIZE_1 0
148 #define SERIAL_DEBUG_PORT_STRIDE_SIZE_4 2
150 #define IGD_DVMT_50_PRE_ALLOC_64M 0x02
151 #define IGD_DVMT_50_PRE_ALLOC_96M 0x03
152 #define IGD_DVMT_50_PRE_ALLOC_128M 0x04
153 #define IGD_DVMT_50_PRE_ALLOC_160M 0x05
154 #define IGD_DVMT_50_PRE_ALLOC_192M 0x06
155 #define IGD_DVMT_50_PRE_ALLOC_224M 0x07
156 #define IGD_DVMT_50_PRE_ALLOC_256M 0x08
157 #define IGD_DVMT_50_PRE_ALLOC_288M 0x09
158 #define IGD_DVMT_50_PRE_ALLOC_320M 0x0a
159 #define IGD_DVMT_50_PRE_ALLOC_352M 0x0b
160 #define IGD_DVMT_50_PRE_ALLOC_384M 0x0c
161 #define IGD_DVMT_50_PRE_ALLOC_416M 0x0d
162 #define IGD_DVMT_50_PRE_ALLOC_448M 0x0e
163 #define IGD_DVMT_50_PRE_ALLOC_480M 0x0f
164 #define IGD_DVMT_50_PRE_ALLOC_512M 0x10
166 #define IGD_APERTURE_SIZE_128M 0x1
167 #define IGD_APERTURE_SIZE_256M 0x2
168 #define IGD_APERTURE_SIZE_512M 0x3
170 #define GTT_SIZE_2M 1
171 #define GTT_SIZE_4M 2
172 #define GTT_SIZE_8M 3
174 #define PRIMARY_VIDEO_ADAPTER_AUTO 0
175 #define PRIMARY_VIDEO_ADAPTER_IGD 2
176 #define PRIMARY_VIDEO_ADAPTER_PCI 3
178 #define PACKAGE_SODIMM 0
179 #define PACKAGE_BGA 1
180 #define PACKAGE_BGA_MIRRORED 2
181 #define PACKAGE_SODIMM_UDIMM_RANK_MIRRORED 3
183 #define PROFILE_WIO2_800_7_8_8 0x1
184 #define PROFILE_WIO2_1066_9_10_10 0x2
185 #define PROFILE_LPDDR3_1066_8_10_10 0x3
186 #define PROFILE_LPDDR3_1333_10_12_12 0x4
187 #define PROFILE_LPDDR3_1600_12_15_15 0x5
188 #define PROFILE_LPDDR3_1866_14_17_17 0x6
189 #define PROFILE_LPDDR3_2133_16_20_20 0x7
190 #define PROFILE_LPDDR4_1066_10_10_10 0x8
191 #define PROFILE_LPDDR4_1600_14_15_15 0x9
192 #define PROFILE_LPDDR4_2133_20_20_20 0xa
193 #define PROFILE_LPDDR4_2400_24_22_22 0xb
194 #define PROFILE_LPDDR4_2666_24_24_24 0xc
195 #define PROFILE_LPDDR4_2933_28_27_27 0xd
196 #define PROFILE_LPDDR4_3200_28_29_29 0xe
197 #define PROFILE_DDR3_1066_6_6_6 0xf
198 #define PROFILE_DDR3_1066_7_7_7 0x10
199 #define PROFILE_DDR3_1066_8_8_8 0x11
200 #define PROFILE_DDR3_1333_7_7_7 0x12
201 #define PROFILE_DDR3_1333_8_8_8 0x13
202 #define PROFILE_DDR3_1333_9_9_9 0x14
203 #define PROFILE_DDR3_1333_10_10_10 0x15
204 #define PROFILE_DDR3_1600_8_8_8 0x16
205 #define PROFILE_DDR3_1600_9_9_9 0x17
206 #define PROFILE_DDR3_1600_10_10_10 0x18
207 #define PROFILE_DDR3_1600_11_11_11 0x19
208 #define PROFILE_DDR3_1866_10_10_10 0x1a
209 #define PROFILE_DDR3_1866_11_11_11 0x1b
210 #define PROFILE_DDR3_1866_12_12_12 0x1c
211 #define PROFILE_DDR3_1866_13_13_13 0x1d
212 #define PROFILE_DDR3_2133_11_11_11 0x1e
213 #define PROFILE_DDR3_2133_12_12_12 0x1f
214 #define PROFILE_DDR3_2133_13_13_13 0x20
215 #define PROFILE_DDR3_2133_14_14_14 0x21
216 #define PROFILE_DDR4_1333_10_10_10 0x22
217 #define PROFILE_DDR4_1600_10_10_10 0x23
218 #define PROFILE_DDR4_1600_11_11_11 0x24
219 #define PROFILE_DDR4_1600_12_12_12 0x25
220 #define PROFILE_DDR4_1866_12_12_12 0x26
221 #define PROFILE_DDR4_1866_13_13_13 0x27
222 #define PROFILE_DDR4_1866_14_14_14 0x28
223 #define PROFILE_DDR4_2133_14_14_14 0x29
224 #define PROFILE_DDR4_2133_15_15_15 0x2a
225 #define PROFILE_DDR4_2133_16_16_16 0x2b
226 #define PROFILE_DDR4_2400_15_15_15 0x2c
227 #define PROFILE_DDR4_2400_16_16_16 0x2d
228 #define PROFILE_DDR4_2400_17_17_17 0x2e
229 #define PROFILE_DDR4_2400_18_18_18 0x2f
231 #define MEMORY_DOWN_NO 0
232 #define MEMORY_DOWN_YES 1
233 #define MEMORY_DOWN_MD_SODIMM 2
234 #define MEMORY_DOWN_LPDDR4 3
236 #define DDR3L_PAGE_SIZE_1KB 1
237 #define DDR3L_PAGE_SIZE_2KB 2
239 #define INTERLEAVED_MODE_DISABLE 0
240 #define INTERLEAVED_MODE_ENABLE 2
242 #define RMT_MODE_DISABLE 0
243 #define RMT_MODE_ENABLE 3
245 #define CHX_DEVICE_WIDTH_X8 0
246 #define CHX_DEVICE_WIDTH_X16 1
247 #define CHX_DEVICE_WIDTH_X32 2
248 #define CHX_DEVICE_WIDTH_X64 3
250 #define CHX_DEVICE_DENSITY_4GB 0
251 #define CHX_DEVICE_DENSITY_6GB 1
252 #define CHX_DEVICE_DENSITY_8GB 2
253 #define CHX_DEVICE_DENSITY_12GB 3
254 #define CHX_DEVICE_DENSITY_16GB 4
255 #define CHX_DEVICE_DENSITY_2GB 5
257 #define CHX_OPTION_RANK_INTERLEAVING 0x1
258 #define CHX_OPTION_BANK_ADDRESS_HASHING_ENABLE 0x2
259 #define CHX_OPTION_CH1_CLK_DISABLE 0x4
260 #define CHX_OPTION_ADDRESS_MAP_2KB 0x10
262 #define CHX_ODT_CONFIG_DDR3_RX_ODT 0x1
263 #define CHX_ODT_CONFIG_DDR4_CA_ODT 0x2
264 #define CHX_ODT_CONFIG_DDR3L_TX_ODT 0x10
266 #define CHX_MODE2N_AUTO 0
267 #define CHX_MODE2N_FORCE 1
269 #define CHX_ODT_LEVELS_CONNECTED_TO_SOC 0x0
270 #define CHX_ODT_LEVELS_HELD_HIGH 0x1
272 #define NPK_EN_DISABLE 0
273 #define NPK_EN_ENABLE 1
274 #define NPK_EN_DEBUGGER 2
275 #define NPK_EN_AUTO 3
277 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_MEMORY 1
278 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_DCI 2
279 #define FW_TRACE_DESTINATION_NPK_NPK_TRACE_TO_BSSB 3
280 #define FW_TRACE_DESTINATION_NPK_TRACE_TO_PTI 4
282 #define MSC_X_WRAP_0 0
283 #define MSC_X_WRAP_1 1
285 #define MSC_X_SIZE_0M 0
286 #define MSC_X_SIZE_1M 1
287 #define MSC_X_SIZE_8M 2
288 #define MSC_X_SIZE_64M 3
289 #define MSC_X_SIZE_128M 4
290 #define MSC_X_SIZE_256M 5
291 #define MSC_X_SIZE_512M 6
292 #define MSC_X_SIZE_1GB 7
295 #define PTI_MODE_x4 1
296 #define PTI_MODE_x8 2
297 #define PTI_MODE_x12 3
298 #define PTI_MODE_x16 4
300 #define PTI_SPEED_FULL 0
301 #define PTI_SPEED_HALF 1
302 #define PTI_SPEED_QUARTER 2