1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014 Google, Inc
13 #include <asm/intel_regs.h>
15 #include <asm/lapic.h>
16 #include <asm/lpc_common.h>
18 #include <asm/arch/model_206ax.h>
19 #include <asm/arch/pch.h>
20 #include <asm/arch/sandybridge.h>
21 #include <linux/bitops.h>
22 #include <linux/delay.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 #define GPIO_BASE 0x48
27 #define BIOS_CTRL 0xdc
29 #define RCBA_AUDIO_CONFIG 0x2030
30 #define RCBA_AUDIO_CONFIG_HDA BIT(31)
31 #define RCBA_AUDIO_CONFIG_MASK 0xfe
33 #ifndef CONFIG_HAVE_FSP
34 static int pch_revision_id = -1;
35 static int pch_type = -1;
38 * pch_silicon_revision() - Read silicon revision ID from the PCH
41 * @return silicon revision ID
43 static int pch_silicon_revision(struct udevice *dev)
47 if (pch_revision_id < 0) {
48 dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
49 pch_revision_id = val;
52 return pch_revision_id;
55 int pch_silicon_type(struct udevice *dev)
60 dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
68 * pch_silicon_supported() - Check if a certain revision is supported
72 * @rev: Minimum required resion
73 * @return 0 if not supported, 1 if supported
75 static int pch_silicon_supported(struct udevice *dev, int type, int rev)
77 int cur_type = pch_silicon_type(dev);
78 int cur_rev = pch_silicon_revision(dev);
82 /* CougarPoint minimum revision */
83 if (cur_type == PCH_TYPE_CPT && cur_rev >= rev)
85 /* PantherPoint any revision */
86 if (cur_type == PCH_TYPE_PPT)
91 /* PantherPoint minimum revision */
92 if (cur_type == PCH_TYPE_PPT && cur_rev >= rev)
100 #define IOBP_RETRY 1000
101 static inline int iobp_poll(void)
103 unsigned try = IOBP_RETRY;
107 data = readl(RCB_REG(IOBPS));
113 printf("IOBP timeout\n");
117 void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
122 /* Set the address */
123 writel(address, RCB_REG(IOBPIRI));
126 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
127 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
129 writel(IOBPS_READ_AX, RCB_REG(IOBPS));
134 data = readl(RCB_REG(IOBPD));
138 /* Check for successful transaction */
139 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) {
140 printf("IOBP read 0x%08x failed\n", address);
144 /* Update the data */
149 if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
150 writel(IOBPS_RW_BX, RCB_REG(IOBPS));
152 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
156 /* Write IOBP data */
157 writel(data, RCB_REG(IOBPD));
162 static int bd82x6x_probe(struct udevice *dev)
164 if (!(gd->flags & GD_FLG_RELOC))
167 /* Cause the SATA device to do its init */
168 uclass_first_device(UCLASS_AHCI, &dev);
172 #endif /* CONFIG_HAVE_FSP */
174 static int bd82x6x_pch_get_spi_base(struct udevice *dev, ulong *sbasep)
178 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
179 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */
180 rcba = rcba & 0xffffc000;
181 *sbasep = rcba + 0x3800;
186 static int bd82x6x_set_spi_protect(struct udevice *dev, bool protect)
188 return lpc_set_spi_protect(dev, BIOS_CTRL, protect);
191 static int bd82x6x_get_gpio_base(struct udevice *dev, u32 *gbasep)
196 * GPIO_BASE moved to its current offset with ICH6, but prior to
197 * that it was unused (or undocumented). Check that it looks
198 * okay: not all ones or zeros.
200 * Note we don't need check bit0 here, because the Tunnel Creek
201 * GPIO base address register bit0 is reserved (read returns 0),
202 * while on the Ivybridge the bit0 is used to indicate it is an
205 dm_pci_read_config32(dev, GPIO_BASE, &base);
206 if (base == 0x00000000 || base == 0xffffffff) {
207 debug("%s: unexpected BASE value\n", __func__);
212 * Okay, I guess we're looking at the right device. The actual
213 * GPIO registers are in the PCI device's I/O space, starting
214 * at the offset that we just read. Bit 0 indicates that it's
215 * an I/O address, not a memory address, so mask that off.
217 *gbasep = base & 1 ? base & ~3 : base & ~15;
222 static int bd82x6x_ioctl(struct udevice *dev, enum pch_req_t req, void *data,
228 case PCH_REQ_HDA_CONFIG:
229 dm_pci_read_config32(dev, PCH_RCBA, &rcba);
230 val = readl(rcba + RCBA_AUDIO_CONFIG);
231 if (!(val & RCBA_AUDIO_CONFIG_HDA))
234 return val & RCBA_AUDIO_CONFIG_MASK;
235 case PCH_REQ_PMBASE_INFO: {
236 struct pch_pmbase_info *pm = data;
239 /* Find the base address of the powermanagement registers */
240 ret = dm_pci_read_config16(dev, 0x40, &pm->base);
244 pm->gpio0_en_ofs = GPE0_EN;
245 pm->pm1_sts_ofs = PM1_STS;
246 pm->pm1_cnt_ofs = PM1_CNT;
255 static const struct pch_ops bd82x6x_pch_ops = {
256 .get_spi_base = bd82x6x_pch_get_spi_base,
257 .set_spi_protect = bd82x6x_set_spi_protect,
258 .get_gpio_base = bd82x6x_get_gpio_base,
259 .ioctl = bd82x6x_ioctl,
262 static const struct udevice_id bd82x6x_ids[] = {
263 { .compatible = "intel,bd82x6x" },
267 U_BOOT_DRIVER(bd82x6x_drv) = {
270 .of_match = bd82x6x_ids,
271 #ifndef CONFIG_HAVE_FSP
272 .probe = bd82x6x_probe,
274 .ops = &bd82x6x_pch_ops,