1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
7 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
17 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
22 #include <bootstage.h>
31 #include <acpi/acpi_s3.h>
32 #include <acpi/acpi_table.h>
34 #include <asm/control_regs.h>
35 #include <asm/coreboot_tables.h>
37 #include <asm/lapic.h>
38 #include <asm/microcode.h>
40 #include <asm/mrccache.h>
44 #include <asm/processor.h>
45 #include <asm/processor-flags.h>
46 #include <asm/interrupt.h>
47 #include <asm/tables.h>
48 #include <linux/compiler.h>
50 DECLARE_GLOBAL_DATA_PTR;
52 #ifndef CONFIG_TPL_BUILD
53 static const char *const x86_vendor_name[] = {
54 [X86_VENDOR_INTEL] = "Intel",
55 [X86_VENDOR_CYRIX] = "Cyrix",
56 [X86_VENDOR_AMD] = "AMD",
57 [X86_VENDOR_UMC] = "UMC",
58 [X86_VENDOR_NEXGEN] = "NexGen",
59 [X86_VENDOR_CENTAUR] = "Centaur",
60 [X86_VENDOR_RISE] = "Rise",
61 [X86_VENDOR_TRANSMETA] = "Transmeta",
62 [X86_VENDOR_NSC] = "NSC",
63 [X86_VENDOR_SIS] = "SiS",
67 int __weak x86_cleanup_before_linux(void)
69 #ifdef CONFIG_BOOTSTAGE_STASH
70 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
71 CONFIG_BOOTSTAGE_STASH_SIZE);
77 int x86_init_cache(void)
83 int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
85 void flush_cache(unsigned long dummy1, unsigned long dummy2)
90 /* Define these functions to allow ehch-hcd to function */
91 void flush_dcache_range(unsigned long start, unsigned long stop)
95 void invalidate_dcache_range(unsigned long start, unsigned long stop)
99 void dcache_enable(void)
104 void dcache_disable(void)
109 void icache_enable(void)
113 void icache_disable(void)
117 int icache_status(void)
122 #ifndef CONFIG_TPL_BUILD
123 const char *cpu_vendor_name(int vendor)
126 name = "<invalid cpu vendor>";
127 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
128 x86_vendor_name[vendor])
129 name = x86_vendor_name[vendor];
135 char *cpu_get_name(char *name)
137 unsigned int *name_as_ints = (unsigned int *)name;
138 struct cpuid_result regs;
142 /* This bit adds up to 48 bytes */
143 for (i = 0; i < 3; i++) {
144 regs = cpuid(0x80000002 + i);
145 name_as_ints[i * 4 + 0] = regs.eax;
146 name_as_ints[i * 4 + 1] = regs.ebx;
147 name_as_ints[i * 4 + 2] = regs.ecx;
148 name_as_ints[i * 4 + 3] = regs.edx;
150 name[CPU_MAX_NAME_LEN - 1] = '\0';
152 /* Skip leading spaces. */
160 int default_print_cpuinfo(void)
162 printf("CPU: %s, vendor %s, device %xh\n",
163 cpu_has_64bit() ? "x86_64" : "x86",
164 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
166 #ifdef CONFIG_HAVE_ACPI_RESUME
167 debug("ACPI previous sleep state: %s\n",
168 acpi_ss_string(gd->arch.prev_sleep_state));
174 void show_boot_progress(int val)
176 outb(val, POST_PORT);
179 #if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
181 * Implement a weak default function for boards that optionally
182 * need to clean up the system before jumping to the kernel.
184 __weak void board_final_cleanup(void)
188 int last_stage_init(void)
190 struct acpi_fadt __maybe_unused *fadt;
192 board_final_cleanup();
194 #ifdef CONFIG_HAVE_ACPI_RESUME
195 fadt = acpi_find_fadt();
197 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
203 #ifdef CONFIG_GENERATE_ACPI_TABLE
204 fadt = acpi_find_fadt();
206 /* Don't touch ACPI hardware on HW reduced platforms */
207 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
209 * Other than waiting for OSPM to request us to switch to ACPI
210 * mode, do it by ourselves, since SMI will not be triggered.
212 enter_acpi_mode(fadt->pm1a_cnt_blk);
220 static int x86_init_cpus(void)
223 debug("Init additional CPUs\n");
229 * This causes the cpu-x86 driver to be probed.
230 * We don't check return value here as we want to allow boards
231 * which have not been converted to use cpu uclass driver to boot.
233 uclass_first_device(UCLASS_CPU, &dev);
244 if (!ll_boot_init()) {
245 uclass_first_device(UCLASS_PCI, &dev);
249 ret = x86_init_cpus();
254 * Set up the northbridge, PCH and LPC if available. Note that these
255 * may have had some limited pre-relocation init if they were probed
256 * before relocation, but this is post relocation.
258 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
259 uclass_first_device(UCLASS_PCH, &dev);
260 uclass_first_device(UCLASS_LPC, &dev);
262 /* Set up pin control if available */
263 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
264 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
269 #ifndef CONFIG_EFI_STUB
270 int reserve_arch(void)
272 #ifdef CONFIG_ENABLE_MRC_CACHE
276 #ifdef CONFIG_SEABIOS
277 high_table_reserve();
280 #ifdef CONFIG_HAVE_ACPI_RESUME
283 #ifdef CONFIG_HAVE_FSP
285 * Save stack address to CMOS so that at next S3 boot,
286 * we can use it as the stack address for fsp_contiue()
289 #endif /* CONFIG_HAVE_FSP */
290 #endif /* CONFIG_HAVE_ACPI_RESUME */
296 long detect_coreboot_table_at(ulong start, ulong size)
301 for (ptr = (void *)start, end = ptr + size; ptr < end; ptr += 4) {
302 if (*ptr == 0x4f49424c) /* "LBIO" */
309 long locate_coreboot_table(void)
313 /* We look for LBIO in the first 4K of RAM and again at 960KB */
314 addr = detect_coreboot_table_at(0x0, 0x1000);
316 addr = detect_coreboot_table_at(0xf0000, 0x1000);