arch/x86/cpu/broadwell/power_state.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * From coreboot src/soc/intel/broadwell/romstage/power_state.c
   4  *
   5  * Copyright (C) 2016 Google, Inc.
   6  */
   7
   8 #include <common.h>
   9 #include <log.h>
  10 #include <pci.h>
  11 #include <asm/io.h>
  12 #include <asm/intel_regs.h>
  13 #include <asm/arch/iomap.h>
  14 #include <asm/arch/lpc.h>
  15 #include <asm/arch/pch.h>
  16 #include <asm/arch/pm.h>
  17
  18 /* Return 0, 3, or 5 to indicate the previous sleep state. */
  19 static int prev_sleep_state(struct chipset_power_state *ps)
  20 {
  21         /* Default to S0. */
  22         int prev_sleep_state = SLEEP_STATE_S0;
  23
  24         if (ps->pm1_sts & WAK_STS) {
  25                 switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) {
  26 #if CONFIG_HAVE_ACPI_RESUME
  27                 case SLP_TYP_S3:
  28                         prev_sleep_state = SLEEP_STATE_S3;
  29                         break;
  30 #endif
  31                 case SLP_TYP_S5:
  32                         prev_sleep_state = SLEEP_STATE_S5;
  33                         break;
  34                 }
  35                 /* Clear SLP_TYP. */
  36                 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
  37         }
  38
  39         if (ps->gen_pmcon3 & (PWR_FLR | SUS_PWR_FLR))
  40                 prev_sleep_state = SLEEP_STATE_S5;
  41
  42         return prev_sleep_state;
  43 }
  44
  45 static void dump_power_state(struct chipset_power_state *ps)
  46 {
  47         debug("PM1_STS:   %04x\n", ps->pm1_sts);
  48         debug("PM1_EN:    %04x\n", ps->pm1_en);
  49         debug("PM1_CNT:   %08x\n", ps->pm1_cnt);
  50         debug("TCO_STS:   %04x %04x\n", ps->tco1_sts, ps->tco2_sts);
  51
  52         debug("GPE0_STS:  %08x %08x %08x %08x\n",
  53               ps->gpe0_sts[0], ps->gpe0_sts[1],
  54               ps->gpe0_sts[2], ps->gpe0_sts[3]);
  55         debug("GPE0_EN:   %08x %08x %08x %08x\n",
  56               ps->gpe0_en[0], ps->gpe0_en[1],
  57               ps->gpe0_en[2], ps->gpe0_en[3]);
  58
  59         debug("GEN_PMCON: %04x %04x %04x\n",
  60               ps->gen_pmcon1, ps->gen_pmcon2, ps->gen_pmcon3);
  61
  62         debug("Previous Sleep State: S%d\n",
  63               ps->prev_sleep_state);
  64 }
  65
  66 /* Fill power state structure from ACPI PM registers */
  67 void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps)
  68 {
  69         ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
  70         ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
  71         ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
  72         ps->tco1_sts = inw(ACPI_BASE_ADDRESS + TCO1_STS);
  73         ps->tco2_sts = inw(ACPI_BASE_ADDRESS + TCO2_STS);
  74         ps->gpe0_sts[0] = inl(ACPI_BASE_ADDRESS + GPE0_STS(0));
  75         ps->gpe0_sts[1] = inl(ACPI_BASE_ADDRESS + GPE0_STS(1));
  76         ps->gpe0_sts[2] = inl(ACPI_BASE_ADDRESS + GPE0_STS(2));
  77         ps->gpe0_sts[3] = inl(ACPI_BASE_ADDRESS + GPE0_STS(3));
  78         ps->gpe0_en[0] = inl(ACPI_BASE_ADDRESS + GPE0_EN(0));
  79         ps->gpe0_en[1] = inl(ACPI_BASE_ADDRESS + GPE0_EN(1));
  80         ps->gpe0_en[2] = inl(ACPI_BASE_ADDRESS + GPE0_EN(2));
  81         ps->gpe0_en[3] = inl(ACPI_BASE_ADDRESS + GPE0_EN(3));
  82
  83         dm_pci_read_config16(pch_dev, GEN_PMCON_1, &ps->gen_pmcon1);
  84         dm_pci_read_config16(pch_dev, GEN_PMCON_2, &ps->gen_pmcon2);
  85         dm_pci_read_config16(pch_dev, GEN_PMCON_3, &ps->gen_pmcon3);
  86
  87         ps->prev_sleep_state = prev_sleep_state(ps);
  88
  89         dump_power_state(ps);
  90 }