arch/x86/cpu/braswell/fsp_configs.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <fdtdec.h>
   8 #include <log.h>
   9 #include <asm/fsp1/fsp_support.h>
  10
  11 DECLARE_GLOBAL_DATA_PTR;
  12
  13 /**
  14  * Override the FSP's Azalia configuration data
  15  *
  16  * @azalia:     pointer to be updated to point to a ROM address where Azalia
  17  *              configuration data is stored
  18  */
  19 __weak void update_fsp_azalia_configs(struct azalia_config **azalia)
  20 {
  21         *azalia = NULL;
  22 }
  23
  24 /**
  25  * Override the FSP's GPIO configuration data
  26  *
  27  * @family:     pointer to be updated to point to a ROM address where GPIO
  28  *              family configuration data is stored
  29  * @pad:        pointer to be updated to point to a ROM address where GPIO
  30  *              pad configuration data is stored
  31  */
  32 __weak void update_fsp_gpio_configs(struct gpio_family **family,
  33                                     struct gpio_pad **pad)
  34 {
  35         *family = NULL;
  36         *pad = NULL;
  37 }
  38
  39 /**
  40  * Override the FSP's configuration data.
  41  * If the device tree does not specify an integer setting, use the default
  42  * provided in Intel's Braswell release FSP/BraswellFsp.bsf file.
  43  */
  44 void fsp_update_configs(struct fsp_config_data *config,
  45                         struct fspinit_rtbuf *rt_buf)
  46 {
  47         struct upd_region *fsp_upd = &config->fsp_upd;
  48         struct memory_upd *memory_upd = &fsp_upd->memory_upd;
  49         struct silicon_upd *silicon_upd = &fsp_upd->silicon_upd;
  50         const void *blob = gd->fdt_blob;
  51         int node;
  52
  53         /* Initialize runtime buffer for fsp_init() */
  54         rt_buf->common.stack_top = config->common.stack_top - 32;
  55         rt_buf->common.boot_mode = config->common.boot_mode;
  56         rt_buf->common.upd_data = &config->fsp_upd;
  57
  58         node = fdt_node_offset_by_compatible(blob, 0, "intel,braswell-fsp");
  59         if (node < 0) {
  60                 debug("%s: Cannot find FSP node\n", __func__);
  61                 return;
  62         }
  63
  64         node = fdt_node_offset_by_compatible(blob, node,
  65                                              "intel,braswell-fsp-memory");
  66         if (node < 0) {
  67                 debug("%s: Cannot find FSP memory node\n", __func__);
  68                 return;
  69         }
  70
  71         /* Override memory UPD contents */
  72         memory_upd->mrc_init_tseg_size = fdtdec_get_int(blob, node,
  73                 "fsp,mrc-init-tseg-size", MRC_INIT_TSEG_SIZE_4MB);
  74         memory_upd->mrc_init_mmio_size = fdtdec_get_int(blob, node,
  75                 "fsp,mrc-init-mmio-size", MRC_INIT_MMIO_SIZE_2048MB);
  76         memory_upd->mrc_init_spd_addr1 = fdtdec_get_int(blob, node,
  77                 "fsp,mrc-init-spd-addr1", 0xa0);
  78         memory_upd->mrc_init_spd_addr2 = fdtdec_get_int(blob, node,
  79                 "fsp,mrc-init-spd-addr2", 0xa2);
  80         memory_upd->igd_dvmt50_pre_alloc = fdtdec_get_int(blob, node,
  81                 "fsp,igd-dvmt50-pre-alloc", IGD_DVMT50_PRE_ALLOC_32MB);
  82         memory_upd->aperture_size = fdtdec_get_int(blob, node,
  83                 "fsp,aperture-size", APERTURE_SIZE_256MB);
  84         memory_upd->gtt_size = fdtdec_get_int(blob, node,
  85                 "fsp,gtt-size", GTT_SIZE_1MB);
  86         memory_upd->legacy_seg_decode = fdtdec_get_bool(blob, node,
  87                 "fsp,legacy-seg-decode");
  88         memory_upd->enable_dvfs = fdtdec_get_bool(blob, node,
  89                 "fsp,enable-dvfs");
  90         memory_upd->memory_type = fdtdec_get_int(blob, node,
  91                 "fsp,memory-type", DRAM_TYPE_DDR3);
  92         memory_upd->enable_ca_mirror = fdtdec_get_bool(blob, node,
  93                 "fsp,enable-ca-mirror");
  94
  95         node = fdt_node_offset_by_compatible(blob, node,
  96                                              "intel,braswell-fsp-silicon");
  97         if (node < 0) {
  98                 debug("%s: Cannot find FSP silicon node\n", __func__);
  99                 return;
 100         }
 101
 102         /* Override silicon UPD contents */
 103         silicon_upd->sdcard_mode = fdtdec_get_int(blob, node,
 104                 "fsp,sdcard-mode", SDCARD_MODE_PCI);
 105         silicon_upd->enable_hsuart0 = fdtdec_get_bool(blob, node,
 106                 "fsp,enable-hsuart0");
 107         silicon_upd->enable_hsuart1 = fdtdec_get_bool(blob, node,
 108                 "fsp,enable-hsuart1");
 109         silicon_upd->enable_azalia = fdtdec_get_bool(blob, node,
 110                 "fsp,enable-azalia");
 111         if (silicon_upd->enable_azalia)
 112                 update_fsp_azalia_configs(&silicon_upd->azalia_cfg_ptr);
 113         silicon_upd->enable_sata = fdtdec_get_bool(blob, node,
 114                 "fsp,enable-sata");
 115         silicon_upd->enable_xhci = fdtdec_get_bool(blob, node,
 116                 "fsp,enable-xhci");
 117         silicon_upd->lpe_mode = fdtdec_get_int(blob, node,
 118                 "fsp,lpe-mode", LPE_MODE_PCI);
 119         silicon_upd->enable_dma0 = fdtdec_get_bool(blob, node,
 120                 "fsp,enable-dma0");
 121         silicon_upd->enable_dma1 = fdtdec_get_bool(blob, node,
 122                 "fsp,enable-dma1");
 123         silicon_upd->enable_i2c0 = fdtdec_get_bool(blob, node,
 124                 "fsp,enable-i2c0");
 125         silicon_upd->enable_i2c1 = fdtdec_get_bool(blob, node,
 126                 "fsp,enable-i2c1");
 127         silicon_upd->enable_i2c2 = fdtdec_get_bool(blob, node,
 128                 "fsp,enable-i2c2");
 129         silicon_upd->enable_i2c3 = fdtdec_get_bool(blob, node,
 130                 "fsp,enable-i2c3");
 131         silicon_upd->enable_i2c4 = fdtdec_get_bool(blob, node,
 132                 "fsp,enable-i2c4");
 133         silicon_upd->enable_i2c5 = fdtdec_get_bool(blob, node,
 134                 "fsp,enable-i2c5");
 135         silicon_upd->enable_i2c6 = fdtdec_get_bool(blob, node,
 136                 "fsp,enable-i2c6");
 137 #ifdef CONFIG_HAVE_VBT
 138         silicon_upd->graphics_config_ptr = CONFIG_VBT_ADDR;
 139 #endif
 140         update_fsp_gpio_configs(&silicon_upd->gpio_familiy_ptr,
 141                                 &silicon_upd->gpio_pad_ptr);
 142         /*
 143          * For Braswell B0 stepping, disable_punit_pwr_config must be set to 1
 144          * otherwise it just hangs in fsp_init().
 145          */
 146         if (gd->arch.x86_mask == 2)
 147                 silicon_upd->disable_punit_pwr_config = 1;
 148         silicon_upd->emmc_mode = fdtdec_get_int(blob, node,
 149                 "fsp,emmc-mode", EMMC_MODE_PCI);
 150         silicon_upd->sata_speed = fdtdec_get_int(blob, node,
 151                 "fsp,sata-speed", SATA_SPEED_GEN3);
 152         silicon_upd->pmic_i2c_bus = fdtdec_get_int(blob, node,
 153                 "fsp,pmic-i2c-bus", 0);
 154         silicon_upd->enable_isp = fdtdec_get_bool(blob, node,
 155                 "fsp,enable-isp");
 156         silicon_upd->isp_pci_dev_config = fdtdec_get_int(blob, node,
 157                 "fsp,isp-pci-dev-config", ISP_PCI_DEV_CONFIG_2);
 158         silicon_upd->turbo_mode = fdtdec_get_bool(blob, node,
 159                 "fsp,turbo-mode");
 160         silicon_upd->pnp_settings = fdtdec_get_int(blob, node,
 161                 "fsp,pnp-settings", PNP_SETTING_POWER_AND_PERF);
 162         silicon_upd->sd_detect_chk = fdtdec_get_bool(blob, node,
 163                 "fsp,sd-detect-chk");
 164 }