arch/x86/cpu/baytrail/acpi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016, Bin Meng <bmeng.cn@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <cpu.h>
   8 #include <dm.h>
   9 #include <log.h>
  10 #include <acpi/acpi_s3.h>
  11 #include <acpi/acpi_table.h>
  12 #include <asm/io.h>
  13 #include <asm/tables.h>
  14 #include <asm/arch/global_nvs.h>
  15 #include <asm/arch/iomap.h>
  16 #include <dm/uclass-internal.h>
  17
  18 void acpi_create_fadt(struct acpi_fadt *fadt, struct acpi_facs *facs,
  19                       void *dsdt)
  20 {
  21         struct acpi_table_header *header = &(fadt->header);
  22         u16 pmbase = ACPI_BASE_ADDRESS;
  23
  24         memset((void *)fadt, 0, sizeof(struct acpi_fadt));
  25
  26         acpi_fill_header(header, "FACP");
  27         header->length = sizeof(struct acpi_fadt);
  28         header->revision = 4;
  29
  30         fadt->firmware_ctrl = (u32)facs;
  31         fadt->dsdt = (u32)dsdt;
  32         fadt->preferred_pm_profile = ACPI_PM_MOBILE;
  33         fadt->sci_int = 9;
  34         fadt->smi_cmd = 0;
  35         fadt->acpi_enable = 0;
  36         fadt->acpi_disable = 0;
  37         fadt->s4bios_req = 0;
  38         fadt->pstate_cnt = 0;
  39         fadt->pm1a_evt_blk = pmbase;
  40         fadt->pm1b_evt_blk = 0x0;
  41         fadt->pm1a_cnt_blk = pmbase + 0x4;
  42         fadt->pm1b_cnt_blk = 0x0;
  43         fadt->pm2_cnt_blk = pmbase + 0x50;
  44         fadt->pm_tmr_blk = pmbase + 0x8;
  45         fadt->gpe0_blk = pmbase + 0x20;
  46         fadt->gpe1_blk = 0;
  47         fadt->pm1_evt_len = 4;
  48         fadt->pm1_cnt_len = 2;
  49         fadt->pm2_cnt_len = 1;
  50         fadt->pm_tmr_len = 4;
  51         fadt->gpe0_blk_len = 8;
  52         fadt->gpe1_blk_len = 0;
  53         fadt->gpe1_base = 0;
  54         fadt->cst_cnt = 0;
  55         fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
  56         fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
  57         fadt->flush_size = 0;
  58         fadt->flush_stride = 0;
  59         fadt->duty_offset = 1;
  60         fadt->duty_width = 0;
  61         fadt->day_alrm = 0x0d;
  62         fadt->mon_alrm = 0x00;
  63         fadt->century = 0x00;
  64         fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
  65         fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
  66                 ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
  67                 ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_RESET_REGISTER |
  68                 ACPI_FADT_PLATFORM_CLOCK;
  69
  70         fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO;
  71         fadt->reset_reg.bit_width = 8;
  72         fadt->reset_reg.bit_offset = 0;
  73         fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
  74         fadt->reset_reg.addrl = IO_PORT_RESET;
  75         fadt->reset_reg.addrh = 0;
  76         fadt->reset_value = SYS_RST | RST_CPU | FULL_RST;
  77
  78         fadt->x_firmware_ctl_l = (u32)facs;
  79         fadt->x_firmware_ctl_h = 0;
  80         fadt->x_dsdt_l = (u32)dsdt;
  81         fadt->x_dsdt_h = 0;
  82
  83         fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  84         fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8;
  85         fadt->x_pm1a_evt_blk.bit_offset = 0;
  86         fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
  87         fadt->x_pm1a_evt_blk.addrl = fadt->pm1a_evt_blk;
  88         fadt->x_pm1a_evt_blk.addrh = 0x0;
  89
  90         fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  91         fadt->x_pm1b_evt_blk.bit_width = 0;
  92         fadt->x_pm1b_evt_blk.bit_offset = 0;
  93         fadt->x_pm1b_evt_blk.access_size = 0;
  94         fadt->x_pm1b_evt_blk.addrl = 0x0;
  95         fadt->x_pm1b_evt_blk.addrh = 0x0;
  96
  97         fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
  98         fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8;
  99         fadt->x_pm1a_cnt_blk.bit_offset = 0;
 100         fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS;
 101         fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk;
 102         fadt->x_pm1a_cnt_blk.addrh = 0x0;
 103
 104         fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 105         fadt->x_pm1b_cnt_blk.bit_width = 0;
 106         fadt->x_pm1b_cnt_blk.bit_offset = 0;
 107         fadt->x_pm1b_cnt_blk.access_size = 0;
 108         fadt->x_pm1b_cnt_blk.addrl = 0x0;
 109         fadt->x_pm1b_cnt_blk.addrh = 0x0;
 110
 111         fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 112         fadt->x_pm2_cnt_blk.bit_width = fadt->pm2_cnt_len * 8;
 113         fadt->x_pm2_cnt_blk.bit_offset = 0;
 114         fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS;
 115         fadt->x_pm2_cnt_blk.addrl = fadt->pm2_cnt_blk;
 116         fadt->x_pm2_cnt_blk.addrh = 0x0;
 117
 118         fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 119         fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
 120         fadt->x_pm_tmr_blk.bit_offset = 0;
 121         fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 122         fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk;
 123         fadt->x_pm_tmr_blk.addrh = 0x0;
 124
 125         fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 126         fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8;
 127         fadt->x_gpe0_blk.bit_offset = 0;
 128         fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS;
 129         fadt->x_gpe0_blk.addrl = fadt->gpe0_blk;
 130         fadt->x_gpe0_blk.addrh = 0x0;
 131
 132         fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO;
 133         fadt->x_gpe1_blk.bit_width = 0;
 134         fadt->x_gpe1_blk.bit_offset = 0;
 135         fadt->x_gpe1_blk.access_size = 0;
 136         fadt->x_gpe1_blk.addrl = 0x0;
 137         fadt->x_gpe1_blk.addrh = 0x0;
 138
 139         header->checksum = table_compute_checksum(fadt, header->length);
 140 }
 141
 142 void acpi_create_gnvs(struct acpi_global_nvs *gnvs)
 143 {
 144         struct udevice *dev;
 145         int ret;
 146
 147         /* at least we have one processor */
 148         gnvs->pcnt = 1;
 149         /* override the processor count with actual number */
 150         ret = uclass_find_first_device(UCLASS_CPU, &dev);
 151         if (ret == 0 && dev != NULL) {
 152                 ret = cpu_get_count(dev);
 153                 if (ret > 0)
 154                         gnvs->pcnt = ret;
 155         }
 156
 157         /* determine whether internal uart is on */
 158         if (IS_ENABLED(CONFIG_INTERNAL_UART))
 159                 gnvs->iuart_en = 1;
 160         else
 161                 gnvs->iuart_en = 0;
 162 }
 163
 164 #ifdef CONFIG_HAVE_ACPI_RESUME
 165 /*
 166  * The following two routines are called at a very early stage, even before
 167  * FSP 2nd phase API fsp_init() is called. Registers off ACPI_BASE_ADDRESS
 168  * and PMC_BASE_ADDRESS are accessed, so we need make sure the base addresses
 169  * of these two blocks are programmed by either U-Boot or FSP.
 170  *
 171  * It has been verified that 1st phase API (see arch/x86/lib/fsp1/fsp_car.S)
 172  * on Intel BayTrail SoC already initializes these two base addresses so
 173  * we are safe to access these registers here.
 174  */
 175
 176 enum acpi_sleep_state chipset_prev_sleep_state(void)
 177 {
 178         u32 pm1_sts;
 179         u32 pm1_cnt;
 180         u32 gen_pmcon1;
 181         enum acpi_sleep_state prev_sleep_state = ACPI_S0;
 182
 183         /* Read Power State */
 184         pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
 185         pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 186         gen_pmcon1 = readl(PMC_BASE_ADDRESS + GEN_PMCON1);
 187
 188         debug("PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
 189               pm1_sts, pm1_cnt, gen_pmcon1);
 190
 191         if (pm1_sts & WAK_STS)
 192                 prev_sleep_state = acpi_sleep_from_pm1(pm1_cnt);
 193
 194         if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR))
 195                 prev_sleep_state = ACPI_S5;
 196
 197         return prev_sleep_state;
 198 }
 199
 200 void chipset_clear_sleep_state(void)
 201 {
 202         u32 pm1_cnt;
 203
 204         pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 205         outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT);
 206 }
 207 #endif