1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2019 Google LLC
8 #include <dt-structs.h>
11 #include <asm/intel_pinctrl.h>
12 #include <asm/intel_regs.h>
14 #include <asm/arch/systemagent.h>
17 * struct apl_hostbridge_platdata - platform data for hostbridge
19 * @dtplat: Platform data for of-platdata
20 * @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
21 * @early_pads_count: Number of pads to process
22 * @pciex_region_size: BAR length in bytes
23 * @bdf: Bus/device/function of hostbridge
25 struct apl_hostbridge_platdata {
26 #if CONFIG_IS_ENABLED(OF_PLATDATA)
27 struct dtd_intel_apl_hostbridge dtplat;
31 uint pciex_region_size;
37 PCIEXBAR_LENGTH_256MB = 0,
38 PCIEXBAR_LENGTH_128MB,
41 PCIEXBAR_PCIEXBAREN = 1 << 0,
43 TSEG = 0xb8, /* TSEG base */
46 static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
48 struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
49 struct udevice *pinctrl;
52 ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
54 return log_msg_ret("no hostbridge pinctrl", ret);
56 return pinctrl_config_pads(pinctrl, plat->early_pads,
57 plat->early_pads_count);
60 static int apl_hostbridge_early_init(struct udevice *dev)
62 struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
68 /* Set up the MCHBAR */
69 pci_x86_read_config(plat->bdf, MCHBAR, &base, PCI_SIZE_32);
70 base = MCH_BASE_ADDRESS;
71 pci_x86_write_config(plat->bdf, MCHBAR, base | 1, PCI_SIZE_32);
74 * The PCIEXBAR is assumed to live in the memory mapped IO space under
77 pci_x86_write_config(plat->bdf, PCIEXBAR + 4, 0, PCI_SIZE_32);
79 switch (plat->pciex_region_size >> 20) {
82 region_size = PCIEXBAR_LENGTH_256MB;
85 region_size = PCIEXBAR_LENGTH_128MB;
88 region_size = PCIEXBAR_LENGTH_64MB;
92 reg = CONFIG_MMCONF_BASE_ADDRESS | (region_size << 1)
93 | PCIEXBAR_PCIEXBAREN;
94 pci_x86_write_config(plat->bdf, PCIEXBAR, reg, PCI_SIZE_32);
97 * TSEG defines the base of SMM range. BIOS determines the base
98 * of TSEG memory which must be at or below Graphics base of GTT
99 * Stolen memory, hence its better to clear TSEG register early
100 * to avoid power on default non-zero value (if any).
102 pci_x86_write_config(plat->bdf, TSEG, 0, PCI_SIZE_32);
104 ret = apl_hostbridge_early_init_pinctrl(dev);
106 return log_msg_ret("pinctrl", ret);
111 static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
113 struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
114 struct udevice *pinctrl;
118 * The host bridge holds the early pad data needed to get through TPL.
119 * This is a small amount of data, enough to fit in TPL, so we keep it
120 * separate from the full pad data, stored in the fsp-s subnode. That
121 * subnode is not present in TPL, to save space.
123 ret = uclass_first_device_err(UCLASS_PINCTRL, &pinctrl);
125 return log_msg_ret("no hostbridge PINCTRL", ret);
126 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
129 /* Get length of PCI Express Region */
130 plat->pciex_region_size = dev_read_u32_default(dev, "pciex-region-size",
133 root = pci_get_devfn(dev);
135 return log_msg_ret("Cannot get host-bridge PCI address", root);
138 ret = pinctrl_read_pads(pinctrl, dev_ofnode(dev), "early-pads",
139 &plat->early_pads, &plat->early_pads_count);
141 return log_msg_ret("early-pads", ret);
143 struct dtd_intel_apl_hostbridge *dtplat = &plat->dtplat;
146 plat->pciex_region_size = dtplat->pciex_region_size;
147 plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
149 /* Assume that if everything is 0, it is empty */
150 plat->early_pads = dtplat->early_pads;
151 size = ARRAY_SIZE(dtplat->early_pads);
152 plat->early_pads_count = pinctrl_count_pads(pinctrl, plat->early_pads,
160 static int apl_hostbridge_probe(struct udevice *dev)
162 if (spl_phase() == PHASE_TPL)
163 return apl_hostbridge_early_init(dev);
168 static const struct udevice_id apl_hostbridge_ids[] = {
169 { .compatible = "intel,apl-hostbridge" },
173 U_BOOT_DRIVER(apl_hostbridge_drv) = {
174 .name = "intel_apl_hostbridge",
175 .id = UCLASS_NORTHBRIDGE,
176 .of_match = apl_hostbridge_ids,
177 .ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
178 .probe = apl_hostbridge_probe,
179 .platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),