1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
10 #include <asm/arch/iomap.h>
11 #include <asm/arch/fsp_bindings.h>
12 #include <asm/fsp2/fsp_internal.h>
13 #include <dm/uclass-internal.h>
15 int fspm_update_config(struct udevice *dev, struct fspm_upd *upd)
17 struct fsp_m_config *cfg = &upd->config;
18 struct fspm_arch_upd *arch = &upd->arch;
21 arch->nvs_buffer_ptr = NULL;
22 prepare_mrc_cache(upd);
23 arch->stack_base = (void *)0xfef96000;
24 arch->boot_loader_tolum_size = 0;
25 arch->boot_mode = FSP_BOOT_WITH_FULL_CONFIGURATION;
27 node = dev_ofnode(dev);
28 if (!ofnode_valid(node))
29 return log_msg_ret("fsp-m settings", -ENOENT);
31 return fsp_m_update_config_from_dtb(node, cfg);
35 * The FSP-M binary appears to break the SPI controller. It can be fixed by
36 * writing the BAR again, so do that here
38 int fspm_done(struct udevice *dev)
43 /* Don't probe the device, since that reads the BAR */
44 ret = uclass_find_first_device(UCLASS_SPI, &spi);
46 return log_msg_ret("SPI", ret);
48 return log_msg_ret("no SPI", -ENODEV);
50 dm_pci_write_config32(spi, PCI_BASE_ADDRESS_0,
51 IOMAP_SPI_BASE | PCI_BASE_ADDRESS_SPACE_MEMORY);