arch/powerpc/dts/p5040.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P5040 Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2012 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e5500_power_isa.dtsi"
  12
  13 / {
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16         interrupt-parent = <&mpic>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: PowerPC,e5500@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         fsl,portid-mapping = <0x80000000>;
  26                 };
  27                 cpu1: PowerPC,e5500@1 {
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         fsl,portid-mapping = <0x40000000>;
  31                 };
  32                 cpu2: PowerPC,e5500@2 {
  33                         device_type = "cpu";
  34                         reg = <2>;
  35                         fsl,portid-mapping = <0x20000000>;
  36                 };
  37                 cpu3: PowerPC,e5500@3 {
  38                         device_type = "cpu";
  39                         reg = <3>;
  40                         fsl,portid-mapping = <0x10000000>;
  41                 };
  42         };
  43
  44         soc: soc@ffe000000 {
  45                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  46                 reg = <0xf 0xfe000000 0 0x00001000>;
  47                 #address-cells = <1>;
  48                 #size-cells = <1>;
  49                 device_type = "soc";
  50                 compatible = "simple-bus";
  51
  52                 mpic: pic@40000 {
  53                         interrupt-controller;
  54                         #address-cells = <0>;
  55                         #interrupt-cells = <4>;
  56                         reg = <0x40000 0x40000>;
  57                         compatible = "fsl,mpic", "chrp,open-pic";
  58                         device_type = "open-pic";
  59                         clock-frequency = <0x0>;
  60                 };
  61
  62                 usb@210000 {
  63                         compatible = "fsl-usb2-mph";
  64                         reg = <0x210000 0x1000>;
  65                         phy_type = "utmi";
  66                 };
  67
  68                 usb@211000 {
  69                         compatible = "fsl-usb2-dr";
  70                         reg = <0x211000 0x1000>;
  71                         phy_type = "utmi";
  72                 };
  73
  74                 sata: sata@220000 {
  75                         compatible = "fsl,pq-sata-v2";
  76                         reg = <0x220000 0x1000>;
  77                         interrupts = <68 0x2 0 0>;
  78                         sata-offset = <0x1000>;
  79                         sata-number = <2>;
  80                         sata-fpdma = <0>;
  81                 };
  82
  83                 esdhc: esdhc@114000 {
  84                         compatible = "fsl,esdhc";
  85                         reg = <0x114000 0x1000>;
  86                         clock-frequency = <0>;
  87                 };
  88
  89                 /include/ "qoriq-i2c-0.dtsi"
  90                 /include/ "qoriq-i2c-1.dtsi"
  91         };
  92
  93         pcie@ffe200000 {
  94                 compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
  95                 reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
  96                 law_trgt_if = <0>;
  97                 #address-cells = <3>;
  98                 #size-cells = <2>;
  99                 device_type = "pci";
 100                 bus-range = <0x0 0xff>;
 101                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
 102                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 103         };
 104
 105         pcie@ffe201000 {
 106                 compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
 107                 reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
 108                 law_trgt_if = <1>;
 109                 #address-cells = <3>;
 110                 #size-cells = <2>;
 111                 device_type = "pci";
 112                 bus-range = <0x0 0xff>;
 113                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
 114                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
 115         };
 116
 117         pcie@ffe202000 {
 118                 compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
 119                 reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
 120                 law_trgt_if = <2>;
 121                 #address-cells = <3>;
 122                 #size-cells = <2>;
 123                 device_type = "pci";
 124                 bus-range = <0x0 0xff>;
 125                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
 126                           0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
 127         };
 128 };