arch/powerpc/dts/p4080.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
   4  *
   5  * Copyright 2011 - 2015 Freescale Semiconductor Inc.
   6  * Copyright 2019-2020 NXP
   7  */
   8
   9 /dts-v1/;
  10
  11 /include/ "e500mc_power_isa.dtsi"
  12
  13 / {
  14         compatible = "fsl,P4080";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&mpic>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: PowerPC,e500mc@0 {
  24                         device_type = "cpu";
  25                         reg = <0>;
  26                         fsl,portid-mapping = <0x80000000>;
  27                 };
  28                 cpu1: PowerPC,e500mc@1 {
  29                         device_type = "cpu";
  30                         reg = <1>;
  31                         fsl,portid-mapping = <0x40000000>;
  32                 };
  33                 cpu2: PowerPC,e500mc@2 {
  34                         device_type = "cpu";
  35                         reg = <2>;
  36                         fsl,portid-mapping = <0x20000000>;
  37                 };
  38                 cpu3: PowerPC,e500mc@3 {
  39                         device_type = "cpu";
  40                         reg = <3>;
  41                         fsl,portid-mapping = <0x10000000>;
  42                 };
  43                 cpu4: PowerPC,e500mc@4 {
  44                         device_type = "cpu";
  45                         reg = <4>;
  46                         fsl,portid-mapping = <0x08000000>;
  47                 };
  48                 cpu5: PowerPC,e500mc@5 {
  49                         device_type = "cpu";
  50                         reg = <5>;
  51                         fsl,portid-mapping = <0x04000000>;
  52                 };
  53                 cpu6: PowerPC,e500mc@6 {
  54                         device_type = "cpu";
  55                         reg = <6>;
  56                         fsl,portid-mapping = <0x02000000>;
  57                 };
  58                 cpu7: PowerPC,e500mc@7 {
  59                         device_type = "cpu";
  60                         reg = <7>;
  61                         fsl,portid-mapping = <0x01000000>;
  62                 };
  63         };
  64
  65         soc: soc@ffe000000 {
  66                 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  67                 reg = <0xf 0xfe000000 0 0x00001000>;
  68                 #address-cells = <1>;
  69                 #size-cells = <1>;
  70                 device_type = "soc";
  71                 compatible = "simple-bus";
  72
  73                 mpic: pic@40000 {
  74                         interrupt-controller;
  75                         #address-cells = <0>;
  76                         #interrupt-cells = <4>;
  77                         reg = <0x40000 0x40000>;
  78                         compatible = "fsl,mpic", "chrp,open-pic";
  79                         device_type = "open-pic";
  80                         clock-frequency = <0x0>;
  81                 };
  82
  83                 esdhc: esdhc@114000 {
  84                         compatible = "fsl,esdhc";
  85                         reg = <0x114000 0x1000>;
  86                         clock-frequency = <0>;
  87                 };
  88
  89                 usb0@210000 {
  90                         compatible = "fsl-usb2-mph";
  91                         reg = <0x210000 0x1000>;
  92                         phy_type = "ulpi";
  93                 };
  94
  95                 usb1@211000 {
  96                         compatible = "fsl-usb2-dr";
  97                         reg = <0x211000 0x1000>;
  98                         phy_type = "ulpi";
  99                 };
 100                 /include/ "qoriq-i2c-0.dtsi"
 101                 /include/ "qoriq-i2c-1.dtsi"
 102         };
 103
 104         pcie@ffe200000 {
 105                 compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
 106                 reg = <0xf 0xfe200000 0x0 0x1000>;   /* registers */
 107                 law_trgt_if = <0>;
 108                 #address-cells = <3>;
 109                 #size-cells = <2>;
 110                 device_type = "pci";
 111                 bus-range = <0x0 0xff>;
 112                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000   /* downstream I/O */
 113                           0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
 114         };
 115
 116         pcie@ffe201000 {
 117                 compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
 118                 reg = <0xf 0xfe201000 0x0 0x1000>;   /* registers */
 119                 law_trgt_if = <1>;
 120                 #address-cells = <3>;
 121                 #size-cells = <2>;
 122                 device_type = "pci";
 123                 bus-range = <0x0 0xff>;
 124                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000   /* downstream I/O */
 125                           0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
 126         };
 127
 128         pcie@ffe202000 {
 129                 compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq";
 130                 reg = <0xf 0xfe202000 0x0 0x1000>;   /* registers */
 131                 law_trgt_if = <2>;
 132                 #address-cells = <3>;
 133                 #size-cells = <2>;
 134                 device_type = "pci";
 135                 bus-range = <0x0 0xff>;
 136                 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000   /* downstream I/O */
 137                           0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
 138         };
 139 };