1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * P3041 Silicon/SoC Device Tree Source (pre include)
5 * Copyright 2010 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019-2020 NXP
11 /include/ "e500mc_power_isa.dtsi"
14 compatible = "fsl,P3041";
17 interrupt-parent = <&mpic>;
23 cpu0: PowerPC,e500mc@0 {
26 fsl,portid-mapping = <0x80000000>;
28 cpu1: PowerPC,e500mc@1 {
31 fsl,portid-mapping = <0x40000000>;
33 cpu2: PowerPC,e500mc@2 {
36 fsl,portid-mapping = <0x20000000>;
38 cpu3: PowerPC,e500mc@3 {
41 fsl,portid-mapping = <0x10000000>;
46 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
47 reg = <0xf 0xfe000000 0 0x00001000>;
51 compatible = "simple-bus";
56 #interrupt-cells = <4>;
57 reg = <0x40000 0x40000>;
58 compatible = "fsl,mpic", "chrp,open-pic";
59 device_type = "open-pic";
60 clock-frequency = <0x0>;
64 compatible = "fsl-usb2-mph";
65 reg = <0x210000 0x1000>;
70 compatible = "fsl-usb2-dr";
71 reg = <0x211000 0x1000>;
76 compatible = "fsl,pq-sata-v2";
77 reg = <0x220000 0x1000>;
78 interrupts = <68 0x2 0 0>;
79 sata-offset = <0x1000>;
85 compatible = "fsl,esdhc";
86 reg = <0x114000 0x1000>;
87 clock-frequency = <0>;
89 /include/ "qoriq-i2c-0.dtsi"
90 /include/ "qoriq-i2c-1.dtsi"
94 compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
95 reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
100 bus-range = <0x0 0xff>;
101 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
102 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
106 compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
107 reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
109 #address-cells = <3>;
112 bus-range = <0x0 0xff>;
113 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
114 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
118 compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
119 reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
121 #address-cells = <3>;
124 bus-range = <0x0 0xff>;
125 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
126 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
130 compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
131 reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
133 #address-cells = <3>;
136 bus-range = <0x0 0xff>;
137 ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
138 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */