arch/powerpc/dts/p1020-post.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR X11
   2 /*
   3  * P1020 Silicon/SoC Device Tree Source (post include)
   4  *
   5  * Copyright 2013 Freescale Semiconductor Inc.
   6  * Copyright 2019 NXP
   7  */
   8
   9 &soc {
  10         #address-cells = <1>;
  11         #size-cells = <1>;
  12         device_type = "soc";
  13         compatible = "fsl,p1020-immr", "simple-bus";
  14         bus-frequency = <0x0>;
  15
  16         usb@22000 {
  17                 compatible = "fsl-usb2-dr";
  18                 reg = <0x22000 0x1000>;
  19                 phy_type = "ulpi";
  20         };
  21
  22         usb@23000 {
  23                 compatible = "fsl-usb2-dr";
  24                 reg = <0x23000 0x1000>;
  25                 phy_type = "ulpi";
  26         };
  27
  28         mpic: pic@40000 {
  29                 interrupt-controller;
  30                 #address-cells = <0>;
  31                 #interrupt-cells = <4>;
  32                 reg = <0x40000 0x40000>;
  33                 compatible = "fsl,mpic";
  34                 device_type = "open-pic";
  35                 big-endian;
  36                 single-cpu-affinity;
  37                 last-interrupt-source = <255>;
  38         };
  39
  40         esdhc: esdhc@2e000 {
  41                 compatible = "fsl,esdhc";
  42                 reg = <0x2e000 0x1000>;
  43                 /* Filled in by U-Boot */
  44                 clock-frequency = <0>;
  45         };
  46
  47         /include/ "pq3-i2c-0.dtsi"
  48         /include/ "pq3-i2c-1.dtsi"
  49 };
  50
  51 /* PCIe controller base address 0x9000 */
  52 &pci1 {
  53         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  54         law_trgt_if = <1>;
  55         #address-cells = <3>;
  56         #size-cells = <2>;
  57         device_type = "pci";
  58         bus-range = <0x0 0xff>;
  59 };
  60
  61 /* PCIe controller base address 0xa000 */
  62 &pci0 {
  63         compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  64         law_trgt_if = <2>;
  65         #address-cells = <3>;
  66         #size-cells = <2>;
  67         device_type = "pci";
  68         bus-range = <0x0 0xff>;
  69 };