2 * Adapted for Motorola MPC8560 chips
3 * Xianghua Xiao <x.xiao@motorola.com>
5 * This file is based on "arch/powerpc/8260_io/commproc.c" - here is it's
8 * General Purpose functions for the global management of the
9 * 8220 Communication Processor Module.
10 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
13 * Copyright (c) 2003 Motorola,Inc.
15 * In addition to the individual control of the communication
16 * channels, there are a few functions that globally affect the
17 * communication processor.
19 * Buffer descriptors must be allocated from the dual ported memory
20 * space. The allocator for that is here. When the communication
21 * process is reset, we reclaim the memory available. There is
22 * currently no deallocator for this memory.
25 #include <asm-offsets.h>
26 #include <asm/cpm_85xx.h>
28 DECLARE_GLOBAL_DATA_PTR;
31 * because we have stack and init data in dual port ram
32 * we must reduce the size
34 #undef CPM_DATAONLY_SIZE
35 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
40 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
43 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
45 /* Reclaim the DP memory for our use.
47 gd->arch.dp_alloc_base = CPM_DATAONLY_BASE;
48 gd->arch.dp_alloc_top = gd->arch.dp_alloc_base + CPM_DATAONLY_SIZE;
53 cpm->im_cpm_cp.cpcr = CPM_CR_RST;
55 do { /* Spin until command processed */
56 __asm__ __volatile__ ("eieio");
57 } while ((cpm->im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
60 /* Allocate some memory from the dual ported ram.
61 * To help protocols with object alignment restrictions, we do that
65 m8560_cpm_dpalloc(uint size, uint align)
67 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
72 align_mask = align - 1;
73 savebase = gd->arch.dp_alloc_base;
75 off = gd->arch.dp_alloc_base & align_mask;
77 gd->arch.dp_alloc_base += (align - off);
79 if ((off = size & align_mask) != 0)
82 if ((gd->arch.dp_alloc_base + size) >= gd->arch.dp_alloc_top) {
83 gd->arch.dp_alloc_base = savebase;
84 panic("m8560_cpm_dpalloc: ran out of dual port ram!");
87 retloc = gd->arch.dp_alloc_base;
88 gd->arch.dp_alloc_base += size;
90 memset((void *)&(cpm->im_dprambase[retloc]), 0, size);
95 /* We also own one page of host buffer space for the allocation of
96 * UART "fifos" and the like.
99 m8560_cpm_hostalloc(uint size, uint align)
101 /* the host might not even have RAM yet - just use dual port RAM */
102 return (m8560_cpm_dpalloc(size, align));
105 /* Set a baud rate generator. This needs lots of work. There are
106 * eight BRGs, which can be connected to the CPM channels or output
107 * as clocks. The BRGs are in two different block of internal
108 * memory mapped space.
109 * The baud rate clock is the system clock divided by something.
110 * It was set up long ago during the initial boot phase and is
112 * Baud rate clocks are zero-based in the driver code (as that maps
113 * to port numbers). Documentation uses 1-based numbering.
115 #define BRG_INT_CLK gd->arch.brg_clk
116 #define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
118 /* This function is used by UARTS, or anything else that uses a 16x
122 m8560_cpm_setbrg(uint brg, uint rate)
124 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
127 /* This is good enough to get SMCs running.....
130 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
133 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
137 *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
140 /* This function is used to set high speed synchronous baud rate
144 m8560_cpm_fastbrg(uint brg, uint rate, int div16)
146 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
149 /* This is good enough to get SMCs running.....
152 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
155 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
159 *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
161 *bp |= CPM_BRG_DIV16;
164 /* This function is used to set baud rate generators using an external
165 * clock source and 16x oversampling.
169 m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
171 volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
175 bp = (uint *)&(cpm->im_cpm_brg1.brgc1);
178 bp = (uint *)&(cpm->im_cpm_brg2.brgc5);
182 *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
184 *bp |= CPM_BRG_EXTC_CLK3_9;
186 *bp |= CPM_BRG_EXTC_CLK5_15;