arch/powerpc/cpu/mpc83xx/speed.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2000-2002
   4  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5  *
   6  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   7  */
   8
   9 #ifndef CONFIG_CLK_MPC83XX
  10
  11 #include <common.h>
  12 #include <clock_legacy.h>
  13 #include <mpc83xx.h>
  14 #include <command.h>
  15 #include <vsprintf.h>
  16 #include <asm/processor.h>
  17
  18 DECLARE_GLOBAL_DATA_PTR;
  19
  20 /* ----------------------------------------------------------------- */
  21
  22 typedef enum {
  23         _unk,
  24         _off,
  25         _byp,
  26         _x8,
  27         _x4,
  28         _x2,
  29         _x1,
  30         _1x,
  31         _1_5x,
  32         _2x,
  33         _2_5x,
  34         _3x
  35 } mult_t;
  36
  37 typedef struct {
  38         mult_t core_csb_ratio;
  39         mult_t vco_divider;
  40 } corecnf_t;
  41
  42 static corecnf_t corecnf_tab[] = {
  43         {_byp, _byp},           /* 0x00 */
  44         {_byp, _byp},           /* 0x01 */
  45         {_byp, _byp},           /* 0x02 */
  46         {_byp, _byp},           /* 0x03 */
  47         {_byp, _byp},           /* 0x04 */
  48         {_byp, _byp},           /* 0x05 */
  49         {_byp, _byp},           /* 0x06 */
  50         {_byp, _byp},           /* 0x07 */
  51         {_1x, _x2},             /* 0x08 */
  52         {_1x, _x4},             /* 0x09 */
  53         {_1x, _x8},             /* 0x0A */
  54         {_1x, _x8},             /* 0x0B */
  55         {_1_5x, _x2},           /* 0x0C */
  56         {_1_5x, _x4},           /* 0x0D */
  57         {_1_5x, _x8},           /* 0x0E */
  58         {_1_5x, _x8},           /* 0x0F */
  59         {_2x, _x2},             /* 0x10 */
  60         {_2x, _x4},             /* 0x11 */
  61         {_2x, _x8},             /* 0x12 */
  62         {_2x, _x8},             /* 0x13 */
  63         {_2_5x, _x2},           /* 0x14 */
  64         {_2_5x, _x4},           /* 0x15 */
  65         {_2_5x, _x8},           /* 0x16 */
  66         {_2_5x, _x8},           /* 0x17 */
  67         {_3x, _x2},             /* 0x18 */
  68         {_3x, _x4},             /* 0x19 */
  69         {_3x, _x8},             /* 0x1A */
  70         {_3x, _x8},             /* 0x1B */
  71 };
  72
  73 /* ----------------------------------------------------------------- */
  74
  75 /*
  76  *
  77  */
  78 int get_clocks(void)
  79 {
  80         volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  81         u32 pci_sync_in;
  82         u8 spmf;
  83         u8 clkin_div;
  84         u32 sccr;
  85         u32 corecnf_tab_index;
  86         u8 corepll;
  87         u32 lcrr;
  88
  89         u32 csb_clk;
  90 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
  91         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
  92         u32 tsec1_clk;
  93         u32 tsec2_clk;
  94         u32 usbdr_clk;
  95 #elif defined(CONFIG_ARCH_MPC8309)
  96         u32 usbdr_clk;
  97 #endif
  98 #ifdef CONFIG_ARCH_MPC834X
  99         u32 usbmph_clk;
 100 #endif
 101         u32 core_clk;
 102         u32 i2c1_clk;
 103 #if !defined(CONFIG_ARCH_MPC832X)
 104         u32 i2c2_clk;
 105 #endif
 106 #if defined(CONFIG_ARCH_MPC8315)
 107         u32 tdm_clk;
 108 #endif
 109 #if defined(CONFIG_FSL_ESDHC)
 110         u32 sdhc_clk;
 111 #endif
 112 #if !defined(CONFIG_ARCH_MPC8309)
 113         u32 enc_clk;
 114 #endif
 115         u32 lbiu_clk;
 116         u32 lclk_clk;
 117         u32 mem_clk;
 118 #if defined(CONFIG_ARCH_MPC8360)
 119         u32 mem_sec_clk;
 120 #endif
 121 #if defined(CONFIG_QE)
 122         u32 qepmf;
 123         u32 qepdf;
 124         u32 qe_clk;
 125         u32 brg_clk;
 126 #endif
 127 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 128         defined(CONFIG_ARCH_MPC837X)
 129         u32 pciexp1_clk;
 130         u32 pciexp2_clk;
 131 #endif
 132 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
 133         u32 sata_clk;
 134 #endif
 135
 136         if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 137                 return -1;
 138
 139         clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
 140
 141         if (im->reset.rcwh & HRCWH_PCI_HOST) {
 142 #if defined(CONFIG_SYS_CLK_FREQ)
 143                 pci_sync_in = CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
 144 #else
 145                 pci_sync_in = 0xDEADBEEF;
 146 #endif
 147         } else {
 148 #if defined(CONFIG_83XX_PCICLK)
 149                 pci_sync_in = CONFIG_83XX_PCICLK;
 150 #else
 151                 pci_sync_in = 0xDEADBEEF;
 152 #endif
 153         }
 154
 155         spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
 156         csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
 157
 158         sccr = im->clk.sccr;
 159
 160 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 161         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 162         switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
 163         case 0:
 164                 tsec1_clk = 0;
 165                 break;
 166         case 1:
 167                 tsec1_clk = csb_clk;
 168                 break;
 169         case 2:
 170                 tsec1_clk = csb_clk / 2;
 171                 break;
 172         case 3:
 173                 tsec1_clk = csb_clk / 3;
 174                 break;
 175         default:
 176                 /* unknown SCCR_TSEC1CM value */
 177                 return -2;
 178         }
 179 #endif
 180
 181 #if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
 182         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 183         switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
 184         case 0:
 185                 usbdr_clk = 0;
 186                 break;
 187         case 1:
 188                 usbdr_clk = csb_clk;
 189                 break;
 190         case 2:
 191                 usbdr_clk = csb_clk / 2;
 192                 break;
 193         case 3:
 194                 usbdr_clk = csb_clk / 3;
 195                 break;
 196         default:
 197                 /* unknown SCCR_USBDRCM value */
 198                 return -3;
 199         }
 200 #endif
 201
 202 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
 203         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 204         switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
 205         case 0:
 206                 tsec2_clk = 0;
 207                 break;
 208         case 1:
 209                 tsec2_clk = csb_clk;
 210                 break;
 211         case 2:
 212                 tsec2_clk = csb_clk / 2;
 213                 break;
 214         case 3:
 215                 tsec2_clk = csb_clk / 3;
 216                 break;
 217         default:
 218                 /* unknown SCCR_TSEC2CM value */
 219                 return -4;
 220         }
 221 #elif defined(CONFIG_ARCH_MPC8313)
 222         tsec2_clk = tsec1_clk;
 223
 224         if (!(sccr & SCCR_TSEC1ON))
 225                 tsec1_clk = 0;
 226         if (!(sccr & SCCR_TSEC2ON))
 227                 tsec2_clk = 0;
 228 #endif
 229
 230 #if defined(CONFIG_ARCH_MPC834X)
 231         switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
 232         case 0:
 233                 usbmph_clk = 0;
 234                 break;
 235         case 1:
 236                 usbmph_clk = csb_clk;
 237                 break;
 238         case 2:
 239                 usbmph_clk = csb_clk / 2;
 240                 break;
 241         case 3:
 242                 usbmph_clk = csb_clk / 3;
 243                 break;
 244         default:
 245                 /* unknown SCCR_USBMPHCM value */
 246                 return -5;
 247         }
 248
 249         if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
 250                 /* if USB MPH clock is not disabled and
 251                  * USB DR clock is not disabled then
 252                  * USB MPH & USB DR must have the same rate
 253                  */
 254                 return -6;
 255         }
 256 #endif
 257 #if !defined(CONFIG_ARCH_MPC8309)
 258         switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
 259         case 0:
 260                 enc_clk = 0;
 261                 break;
 262         case 1:
 263                 enc_clk = csb_clk;
 264                 break;
 265         case 2:
 266                 enc_clk = csb_clk / 2;
 267                 break;
 268         case 3:
 269                 enc_clk = csb_clk / 3;
 270                 break;
 271         default:
 272                 /* unknown SCCR_ENCCM value */
 273                 return -7;
 274         }
 275 #endif
 276
 277 #if defined(CONFIG_FSL_ESDHC)
 278         switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
 279         case 0:
 280                 sdhc_clk = 0;
 281                 break;
 282         case 1:
 283                 sdhc_clk = csb_clk;
 284                 break;
 285         case 2:
 286                 sdhc_clk = csb_clk / 2;
 287                 break;
 288         case 3:
 289                 sdhc_clk = csb_clk / 3;
 290                 break;
 291         default:
 292                 /* unknown SCCR_SDHCCM value */
 293                 return -8;
 294         }
 295 #endif
 296 #if defined(CONFIG_ARCH_MPC8315)
 297         switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
 298         case 0:
 299                 tdm_clk = 0;
 300                 break;
 301         case 1:
 302                 tdm_clk = csb_clk;
 303                 break;
 304         case 2:
 305                 tdm_clk = csb_clk / 2;
 306                 break;
 307         case 3:
 308                 tdm_clk = csb_clk / 3;
 309                 break;
 310         default:
 311                 /* unknown SCCR_TDMCM value */
 312                 return -8;
 313         }
 314 #endif
 315
 316 #if defined(CONFIG_ARCH_MPC834X)
 317         i2c1_clk = tsec2_clk;
 318 #elif defined(CONFIG_ARCH_MPC8360)
 319         i2c1_clk = csb_clk;
 320 #elif defined(CONFIG_ARCH_MPC832X)
 321         i2c1_clk = enc_clk;
 322 #elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
 323         i2c1_clk = enc_clk;
 324 #elif defined(CONFIG_FSL_ESDHC)
 325         i2c1_clk = sdhc_clk;
 326 #elif defined(CONFIG_ARCH_MPC837X)
 327         i2c1_clk = enc_clk;
 328 #elif defined(CONFIG_ARCH_MPC8309)
 329         i2c1_clk = csb_clk;
 330 #endif
 331 #if !defined(CONFIG_ARCH_MPC832X)
 332         i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
 333 #endif
 334
 335 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 336         defined(CONFIG_ARCH_MPC837X)
 337         switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
 338         case 0:
 339                 pciexp1_clk = 0;
 340                 break;
 341         case 1:
 342                 pciexp1_clk = csb_clk;
 343                 break;
 344         case 2:
 345                 pciexp1_clk = csb_clk / 2;
 346                 break;
 347         case 3:
 348                 pciexp1_clk = csb_clk / 3;
 349                 break;
 350         default:
 351                 /* unknown SCCR_PCIEXP1CM value */
 352                 return -9;
 353         }
 354
 355         switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
 356         case 0:
 357                 pciexp2_clk = 0;
 358                 break;
 359         case 1:
 360                 pciexp2_clk = csb_clk;
 361                 break;
 362         case 2:
 363                 pciexp2_clk = csb_clk / 2;
 364                 break;
 365         case 3:
 366                 pciexp2_clk = csb_clk / 3;
 367                 break;
 368         default:
 369                 /* unknown SCCR_PCIEXP2CM value */
 370                 return -10;
 371         }
 372 #endif
 373
 374 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
 375         switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
 376         case 0:
 377                 sata_clk = 0;
 378                 break;
 379         case 1:
 380                 sata_clk = csb_clk;
 381                 break;
 382         case 2:
 383                 sata_clk = csb_clk / 2;
 384                 break;
 385         case 3:
 386                 sata_clk = csb_clk / 3;
 387                 break;
 388         default:
 389                 /* unknown SCCR_SATA1CM value */
 390                 return -11;
 391         }
 392 #endif
 393
 394         lbiu_clk = csb_clk *
 395                    (1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 396         lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
 397         switch (lcrr) {
 398         case 2:
 399         case 4:
 400         case 8:
 401                 lclk_clk = lbiu_clk / lcrr;
 402                 break;
 403         default:
 404                 /* unknown lcrr */
 405                 return -12;
 406         }
 407
 408         mem_clk = csb_clk *
 409                   (1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
 410         corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
 411
 412 #if defined(CONFIG_ARCH_MPC8360)
 413         mem_sec_clk = csb_clk * (1 +
 414                        ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
 415 #endif
 416
 417         corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
 418         if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
 419                 /* corecnf_tab_index is too high, possibly wrong value */
 420                 return -11;
 421         }
 422         switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
 423         case _byp:
 424         case _x1:
 425         case _1x:
 426                 core_clk = csb_clk;
 427                 break;
 428         case _1_5x:
 429                 core_clk = (3 * csb_clk) / 2;
 430                 break;
 431         case _2x:
 432                 core_clk = 2 * csb_clk;
 433                 break;
 434         case _2_5x:
 435                 core_clk = (5 * csb_clk) / 2;
 436                 break;
 437         case _3x:
 438                 core_clk = 3 * csb_clk;
 439                 break;
 440         default:
 441                 /* unknown core to csb ratio */
 442                 return -13;
 443         }
 444
 445 #if defined(CONFIG_QE)
 446         qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
 447         qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
 448         qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
 449         brg_clk = qe_clk / 2;
 450 #endif
 451
 452         gd->arch.csb_clk = csb_clk;
 453 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 454         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 455         gd->arch.tsec1_clk = tsec1_clk;
 456         gd->arch.tsec2_clk = tsec2_clk;
 457         gd->arch.usbdr_clk = usbdr_clk;
 458 #elif defined(CONFIG_ARCH_MPC8309)
 459         gd->arch.usbdr_clk = usbdr_clk;
 460 #endif
 461 #if defined(CONFIG_ARCH_MPC834X)
 462         gd->arch.usbmph_clk = usbmph_clk;
 463 #endif
 464 #if defined(CONFIG_ARCH_MPC8315)
 465         gd->arch.tdm_clk = tdm_clk;
 466 #endif
 467 #if defined(CONFIG_FSL_ESDHC)
 468         gd->arch.sdhc_clk = sdhc_clk;
 469 #endif
 470         gd->arch.core_clk = core_clk;
 471         gd->arch.i2c1_clk = i2c1_clk;
 472 #if !defined(CONFIG_ARCH_MPC832X)
 473         gd->arch.i2c2_clk = i2c2_clk;
 474 #endif
 475 #if !defined(CONFIG_ARCH_MPC8309)
 476         gd->arch.enc_clk = enc_clk;
 477 #endif
 478         gd->arch.lbiu_clk = lbiu_clk;
 479         gd->arch.lclk_clk = lclk_clk;
 480         gd->mem_clk = mem_clk;
 481 #if defined(CONFIG_ARCH_MPC8360)
 482         gd->arch.mem_sec_clk = mem_sec_clk;
 483 #endif
 484 #if defined(CONFIG_QE)
 485         gd->arch.qe_clk = qe_clk;
 486         gd->arch.brg_clk = brg_clk;
 487 #endif
 488 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 489         defined(CONFIG_ARCH_MPC837X)
 490         gd->arch.pciexp1_clk = pciexp1_clk;
 491         gd->arch.pciexp2_clk = pciexp2_clk;
 492 #endif
 493 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
 494         gd->arch.sata_clk = sata_clk;
 495 #endif
 496         gd->pci_clk = pci_sync_in;
 497         gd->cpu_clk = gd->arch.core_clk;
 498         gd->bus_clk = gd->arch.csb_clk;
 499         return 0;
 500
 501 }
 502
 503 /********************************************
 504  * get_bus_freq
 505  * return system bus freq in Hz
 506  *********************************************/
 507 ulong get_bus_freq(ulong dummy)
 508 {
 509         return gd->arch.csb_clk;
 510 }
 511
 512 /********************************************
 513  * get_ddr_freq
 514  * return ddr bus freq in Hz
 515  *********************************************/
 516 ulong get_ddr_freq(ulong dummy)
 517 {
 518         return gd->mem_clk;
 519 }
 520
 521 int get_serial_clock(void)
 522 {
 523         return get_bus_freq(0);
 524 }
 525
 526 static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
 527                      char *const argv[])
 528 {
 529         char buf[32];
 530
 531         printf("Clock configuration:\n");
 532         printf("  Core:                %-4s MHz\n",
 533                strmhz(buf, gd->arch.core_clk));
 534         printf("  Coherent System Bus: %-4s MHz\n",
 535                strmhz(buf, gd->arch.csb_clk));
 536 #if defined(CONFIG_QE)
 537         printf("  QE:                  %-4s MHz\n",
 538                strmhz(buf, gd->arch.qe_clk));
 539         printf("  BRG:                 %-4s MHz\n",
 540                strmhz(buf, gd->arch.brg_clk));
 541 #endif
 542         printf("  Local Bus Controller:%-4s MHz\n",
 543                strmhz(buf, gd->arch.lbiu_clk));
 544         printf("  Local Bus:           %-4s MHz\n",
 545                strmhz(buf, gd->arch.lclk_clk));
 546         printf("  DDR:                 %-4s MHz\n", strmhz(buf, gd->mem_clk));
 547 #if defined(CONFIG_ARCH_MPC8360)
 548         printf("  DDR Secondary:       %-4s MHz\n",
 549                strmhz(buf, gd->arch.mem_sec_clk));
 550 #endif
 551 #if !defined(CONFIG_ARCH_MPC8309)
 552         printf("  SEC:                 %-4s MHz\n",
 553                strmhz(buf, gd->arch.enc_clk));
 554 #endif
 555         printf("  I2C1:                %-4s MHz\n",
 556                strmhz(buf, gd->arch.i2c1_clk));
 557 #if !defined(CONFIG_ARCH_MPC832X)
 558         printf("  I2C2:                %-4s MHz\n",
 559                strmhz(buf, gd->arch.i2c2_clk));
 560 #endif
 561 #if defined(CONFIG_ARCH_MPC8315)
 562         printf("  TDM:                 %-4s MHz\n",
 563                strmhz(buf, gd->arch.tdm_clk));
 564 #endif
 565 #if defined(CONFIG_FSL_ESDHC)
 566         printf("  SDHC:                %-4s MHz\n",
 567                strmhz(buf, gd->arch.sdhc_clk));
 568 #endif
 569 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 570         defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
 571         printf("  TSEC1:               %-4s MHz\n",
 572                strmhz(buf, gd->arch.tsec1_clk));
 573         printf("  TSEC2:               %-4s MHz\n",
 574                strmhz(buf, gd->arch.tsec2_clk));
 575         printf("  USB DR:              %-4s MHz\n",
 576                strmhz(buf, gd->arch.usbdr_clk));
 577 #elif defined(CONFIG_ARCH_MPC8309)
 578         printf("  USB DR:              %-4s MHz\n",
 579                strmhz(buf, gd->arch.usbdr_clk));
 580 #endif
 581 #if defined(CONFIG_ARCH_MPC834X)
 582         printf("  USB MPH:             %-4s MHz\n",
 583                strmhz(buf, gd->arch.usbmph_clk));
 584 #endif
 585 #if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
 586         defined(CONFIG_ARCH_MPC837X)
 587         printf("  PCIEXP1:             %-4s MHz\n",
 588                strmhz(buf, gd->arch.pciexp1_clk));
 589         printf("  PCIEXP2:             %-4s MHz\n",
 590                strmhz(buf, gd->arch.pciexp2_clk));
 591 #endif
 592 #if defined(CONFIG_ARCH_MPC837X) || defined(CONFIG_ARCH_MPC8315)
 593         printf("  SATA:                %-4s MHz\n",
 594                strmhz(buf, gd->arch.sata_clk));
 595 #endif
 596         return 0;
 597 }
 598
 599 U_BOOT_CMD(clocks, 1, 0, do_clocks,
 600         "print clock configuration",
 601         "    clocks"
 602 );
 603
 604 #endif