1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2018 Microsemi Corporation
10 int mscc_phy_rd_wr(u8 read,
20 data = (read ? MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(2) : /* Read */
21 MSCC_F_MII_CMD_MIIM_CMD_OPR_FIELD(1) | /* Write */
22 MSCC_F_MII_CMD_MIIM_CMD_WRDATA(*value)); /* value */
26 MSCC_F_MII_CMD_MIIM_CMD_VLD(1) | /* Valid command */
27 MSCC_F_MII_CMD_MIIM_CMD_REGAD(addr) | /* Reg addr */
28 MSCC_F_MII_CMD_MIIM_CMD_PHYAD(miim_addr); /* Miim addr */
30 /* Enqueue MIIM operation to be executed */
31 writel(data, BASE_DEVCPU_GCB + MIIM_MII_CMD(miimdev));
33 /* Wait for MIIM operation to finish */
37 debug("Miim timeout");
40 data = readl(BASE_DEVCPU_GCB + MIIM_MII_STATUS(miimdev));
41 debug("Read status miim(%d): 0x%08x\n", miimdev, data);
42 } while (data & MSCC_F_MII_STATUS_MIIM_STAT_BUSY(1));
45 data = readl(BASE_DEVCPU_GCB + MIIM_MII_DATA(miimdev));
46 if (data & MSCC_M_MII_DATA_MIIM_DATA_SUCCESS) {
47 debug("Read(%d, %d) returned 0x%08x\n",
48 miim_addr, addr, data);
51 *value = MSCC_X_MII_DATA_MIIM_DATA_RDDATA(data);
57 int mscc_phy_rd(u32 miimdev,
62 if (mscc_phy_rd_wr(1, miimdev, miim_addr, addr, value) == 0)
64 debug("Read(%d, %d) returned error\n", miim_addr, addr);
68 int mscc_phy_wr(u32 miimdev,
73 return mscc_phy_rd_wr(0, miimdev, miim_addr, addr, &value);